mirror of
https://github.com/myhdl/myhdl.git
synced 2024-12-14 07:44:38 +08:00
42 lines
1.2 KiB
ReStructuredText
42 lines
1.2 KiB
ReStructuredText
.. _new07:
|
|
|
|
***********************
|
|
What's new in MyHDL 0.7
|
|
***********************
|
|
|
|
Conversion to VHDL/Verilog rewritten with the ``ast`` module
|
|
============================================================
|
|
|
|
The most important code change is a change that hopefully no-one will
|
|
notice :-). The conversion code is now based on the ``ast`` package
|
|
instead of the ``compiler`` package. Since Python 2.6, the
|
|
``compiler`` package is deprecated and replaced by the new ``ast``
|
|
package in the standard library. In Python 3, the ``compiler``
|
|
package is no longer available.
|
|
|
|
This was a considerable effort, spent on re-implementing existing
|
|
behavior instead of on new interesting features. This sound
|
|
unfortunate, but it had to be done with priority. Now the conversion
|
|
code is ready for the future.
|
|
|
|
|
|
Shadow signals
|
|
==============
|
|
|
|
Background
|
|
----------
|
|
|
|
Compared to HDLs such as VHDL and Verilog, MyHDL signals are less
|
|
flexible for structural modeling. For example, slicing a signal
|
|
returns a slice of the current value. For behavioral code, this is
|
|
just fine. However, it implies that you cannot use such as slice in
|
|
structural descriptions. In other words, a signal slice cannot be used
|
|
as a signal.
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|