a9d65c0f87
* 1) added J. Villars code from PR#238 (https://github.com/myhdl/myhdl/pull/328) to augment the `@block` decorator with arguments, initially to keep the generated names simpler especially when nesting `block`s without adding *hdl* code - I modified it a bit using `skipname=False` rather than `keepname=True` as default 2) added _hdlclass.py to support Class Based Design, look at bot test/conversion/general/test_hdlclass.py and test/conversion/general/test_hdlclass2.py This needed the changes of 1) above. * 1) _Signal.py added property `.nbits` for use in HDL iso `len(sig)`, anticipating Structure and Array where `len()` is not what `.nbits` will give you ... added `duplicate(value=None)` method to avoid that ugly `newsig = Signal(oldsig._val)` 2) _block.py minor changes 3)_hdlclass.py removed ForwardPorts resolution as this currently adds a *stray* sig in the .vcd output - even if noe ForwardPorts are present cleaned the code to what is actually working 4) _traceSignals.py The `@block(skipname=True), which is heavily used in Class Based Design, applies `None` as that block-name and this will show up as an additional level in the .vcd which looks ugly and distracting. So reworked this file to skip adding the None-level Also added indents in the .vcd var section, primarily for debugging, but kept this as it looks nice. Introduce f'strings 5) _analyze.py changed UPPER_CASE naming of processe/always into lower case, making the generated signals conform with the producing process/always 6) test_xxxx.py changed @instance with *logic* as function name into *comb* as `logic` has become a reserved Verilog keyword * cleaned test/bugs replacing generator names *logic* and *output* with *comb* as `logic` and `output` have become Verilog reserved keywords * replacing more occurrences of *logic* by either *comb* or *synch* * one *comb* too many :( * added small test_hdlclass0.py to help in debugging updated the 'doc' section -- needs publishing added direct conversion of Class Based Design modules - resulting in lesss boiler-plate code
MyHDL 0.11
What is MyHDL?
MyHDL is a free, open-source package for using Python as a hardware description and verification language.
To find out whether MyHDL can be useful to you, please read:
License
MyHDL is available under the LGPL license. See LICENSE.txt.
Website
The project website is located at http://www.myhdl.org
Documentation
The manual is available on-line:
What's new
To find out what's new in this release, please read:
Installation
It is recommended to install MyHDL (and your project's other dependencies) in a virtualenv.
Installing the latest stable release:
pip install myhdl
Unfortunately the version on PyPI is quite behind the current development status, so you are better off installing the stable master branch directly from this GitHub repository:
pip install git+https://github.com/myhdl/myhdl.git@master
To install a local clone of the repository:
pip install -e path/to/dir
To install a specific commit hash, tag or branch from git:
pip install git+https://github.com/myhdl/myhdl@f696b8
You can test the proper installation as follows:
cd myhdl/test/core
py.test
To install co-simulation support:
Go to the directory cosimulation/<platform> for your target platform
and following the instructions in the README.txt file.