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59 lines
1.0 KiB
Python
59 lines
1.0 KiB
Python
from myhdl import *
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def dffa(q, d, clk, rst):
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@always(clk.posedge, rst.negedge)
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def logic():
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if rst == 0:
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q.next = 0
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else:
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q.next = d
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return logic
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from random import randrange
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def test_dffa():
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q, d, clk, rst = [Signal(bool(0)) for i in range(4)]
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dffa_inst = dffa(q, d, clk, rst)
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@always(delay(10))
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def clkgen():
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clk.next = not clk
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@always(clk.negedge)
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def stimulus():
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d.next = randrange(2)
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@instance
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def rstgen():
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yield delay(5)
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rst.next = 1
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while True:
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yield delay(randrange(500, 1000))
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rst.next = 0
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yield delay(randrange(80, 140))
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rst.next = 1
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return dffa_inst, clkgen, stimulus, rstgen
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def simulate(timesteps):
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tb = traceSignals(test_dffa)
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sim = Simulation(tb)
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sim.run(timesteps)
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simulate(20000)
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def convert():
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q, d, clk, rst = [Signal(bool(0)) for i in range(4)]
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toVerilog(dffa, q, d, clk, rst)
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convert()
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