FPGA/myhdl
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jand b8d77aca7b version check
2003-01-30 17:19:02 +00:00
example
clean-up
2003-01-30 16:34:16 +00:00
myhdl
Top-level test
2003-01-30 12:19:52 +00:00
LICENSE.txt
Added license
2003-01-28 10:13:57 +00:00
MANIFEST.in
Put into a project
2003-01-23 23:21:31 +00:00
setup.py
version check
2003-01-30 17:19:02 +00:00
test.py
Added
2003-01-30 17:00:10 +00:00
Description
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14 MiB
Languages
Python 86.2%
C 5.9%
Verilog 5.8%
VHDL 1.2%
Shell 0.5%
Other 0.4%