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49 lines
734 B
Python
49 lines
734 B
Python
from myhdl import *
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def latch(q, d, g):
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@always_comb
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def logic():
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if g == 1:
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q.next = d
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return logic
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from random import randrange
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def test_latch():
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q, d, g = [Signal(bool(0)) for i in range(3)]
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latch_inst = latch(q, d, g)
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@always(delay(7))
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def dgen():
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d.next = randrange(2)
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@always(delay(41))
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def ggen():
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g.next = randrange(2)
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return latch_inst, dgen, ggen
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def simulate(timesteps):
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tb = traceSignals(test_latch)
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sim = Simulation(tb)
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sim.run(timesteps)
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simulate(20000)
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def convert():
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q, d, g = [Signal(bool(0)) for i in range(3)]
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toVerilog(latch, q, d, g)
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conversion.analyze(latch, q, d, g)
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convert()
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