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37 lines
636 B
Python
37 lines
636 B
Python
import seven_segment
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from myhdl import *
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code = [None] * 10
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for key, val in seven_segment.encoding.items():
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if 0 <= key <= 9:
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code[key] = int(val, 2)
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code = tuple(code)
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def bcd2led(led, bcd, clock):
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""" bcd to seven segment led convertor.
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led: seven segment led output
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bcd: bcd input
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clock: clock input
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"""
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@always(clock.posedge)
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def logic():
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led.next = code[int(bcd)]
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return logic
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def convert():
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led = Signal(intbv(0)[7:])
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bcd = Signal(intbv(0)[4:])
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clock = Signal(False)
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toVerilog(bcd2led, led, bcd, clock)
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toVHDL(bcd2led, led, bcd, clock)
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convert()
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