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https://github.com/myhdl/myhdl.git
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55 lines
1.4 KiB
TeX
55 lines
1.4 KiB
TeX
\documentclass{manual}
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\usepackage{palatino}
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\renewcommand{\ttdefault}{cmtt}
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\renewcommand{\sfdefault}{cmss}
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\newcommand{\myhdl}{{MyHDL}}
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\title{The \myhdl\ manual}
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\input{boilerplate}
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\begin{document}
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\maketitle
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\input{copyright}
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\begin{abstract}
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\noindent
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\myhdl\ is a Python package for using Python as a hardware description
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language. Popular hardware description languages, like Verilog and
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VHDL, are compiled languages. \myhdl\ with Python could be viewed as a
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"scripting language" counterpart of such languages. However, Python is
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more accurately described as a very high level language
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(VHLL). \myhdl\ users have access to the amazing power and elegance of
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Python in their modeling work.
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The key idea behind \myhdl\ is to use Python generators to model the
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concurrency required in hardware descriptions. As generators are a
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recent Python feature, \myhdl\ requires Python 2.2.2. or higher.
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\myhdl\ 0.1 is the initial public release of the package. It can be
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used experiment with high level modeling, and with verification
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techniques such as unit testing.
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In a future release, \myhdl\ will
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hopefully be coupled to hardware simulators for languages such as
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Verilog and VHDL. That would turn \myhdl\ into a powerful hardware
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verification language.
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\end{abstract}
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\tableofcontents
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\input{background.tex}
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\input{informal.tex}
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\input{modeling.tex}
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\input{unittest.tex}
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\input{reference.tex}
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\end{document}
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