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1513a24e18
Updated the MyHDL manual to include the 0.9 what's new in the index and additional verbage in the conversion section on interfaces. This commit is also being used as a test vehicle for the new development flow using git.
97 lines
3.0 KiB
ReStructuredText
97 lines
3.0 KiB
ReStructuredText
.. currentmodule:: myhdl
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.. _new09:
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***********************
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What's new in MyHDL 0.9
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***********************
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Interfaces
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===========
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Rationale
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---------
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Complex designs often have many signals (ports) that are passed to
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different levels of hierarchy. Typically, many of the signals can
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logically be grouped together. Grouping the signals into an
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*interface* simplifies the code, improves efficiency, and reduces
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errors.
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An *interface* is a collection of signals (:class:`Signal`) embedded
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in an class/object as attributes. This provides a natural method
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to group related signals and provides intuitive access through
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attributes. Multiple level of objects and attibutes provides a
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hierarchy of signal structure if desired.
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The following is an example of an *interface* definition::
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class Complex:
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def __init__(self, min=-2, max=2):
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self.real = Signal(intbv(0, min=min, max=max))
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self.imag = Signal(intbv(0, min=min, max=max))
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Previous versions supported *interfaces* for modeling and for
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conversion if the attributes were locally referenced in a MyHDL
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module outside of the `MyHDL generator`_. If the attributes were
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directly referenced in the `MyHDL generator`_ the code would not be
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convertible.
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This features adds the ability to convert attributes that are
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:class:`Signal` and referenced in the `MyHDL generator`_. This is
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an evolution of a useful construct.
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The following
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is an example using the above ``Complex`` interface definition::
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a,b = Complex(-8,8), Complex(-8,8)
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c = Complex(-128,128)
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def complex_multiply(clock, reset, a, b, c):
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@always_seq(clock.posedge, reset=reset)
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def cmult():
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c.real.next = (a.real*b.real) - (a.imag*b.imag)
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c.imag.next = (a.real*b.imag) + (a.imag*b.real)
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return cmult
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Solution
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--------
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The proposed solution is to create unique names for attributes which
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are type :class:`Signal` and used by a `MyHDL generator`_. The
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converter will create a unique name by using the name of the parent
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and the name of the attribute along with the name of the MyHDL module
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instance (if required for uniqueness). The converter will essentially
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replace the "." with an "_" for each *interface* element.
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Even though the target HDLs do not support *interfaces*, MyHDL is
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able to add high-level features that compile during conversion to the
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target HDL (Verilog and VHDL).
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Conversion
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----------
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.. add details of the conversion, what policies are used to name
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.. extend the Signals. Any useful information about the approach
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.. or structure in the converter used.
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Limitations
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-----------
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The current implementation only converts ``Signal`` attributes and
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constants (read-only ints). Other Python structures will not be
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analyzed (e.g. dict) and attributes used as variables will not be
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converted.
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See also
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--------
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For additional information see the original proposal `mep-107`_.
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.. _mep-107: http://http://myhdl.org/doku.php/meps:mep-107
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.. _MyHDL generator: http://docs.myhdl.org/en/latest/manual/reference.html#myhdl-generators-and-trigger-objects
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