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a9d65c0f87
* 1) added J. Villars code from PR#238 (https://github.com/myhdl/myhdl/pull/328) to augment the `@block` decorator with arguments, initially to keep the generated names simpler especially when nesting `block`s without adding *hdl* code - I modified it a bit using `skipname=False` rather than `keepname=True` as default 2) added _hdlclass.py to support Class Based Design, look at bot test/conversion/general/test_hdlclass.py and test/conversion/general/test_hdlclass2.py This needed the changes of 1) above. * 1) _Signal.py added property `.nbits` for use in HDL iso `len(sig)`, anticipating Structure and Array where `len()` is not what `.nbits` will give you ... added `duplicate(value=None)` method to avoid that ugly `newsig = Signal(oldsig._val)` 2) _block.py minor changes 3)_hdlclass.py removed ForwardPorts resolution as this currently adds a *stray* sig in the .vcd output - even if noe ForwardPorts are present cleaned the code to what is actually working 4) _traceSignals.py The `@block(skipname=True), which is heavily used in Class Based Design, applies `None` as that block-name and this will show up as an additional level in the .vcd which looks ugly and distracting. So reworked this file to skip adding the None-level Also added indents in the .vcd var section, primarily for debugging, but kept this as it looks nice. Introduce f'strings 5) _analyze.py changed UPPER_CASE naming of processe/always into lower case, making the generated signals conform with the producing process/always 6) test_xxxx.py changed @instance with *logic* as function name into *comb* as `logic` has become a reserved Verilog keyword * cleaned test/bugs replacing generator names *logic* and *output* with *comb* as `logic` and `output` have become Verilog reserved keywords * replacing more occurrences of *logic* by either *comb* or *synch* * one *comb* too many :( * added small test_hdlclass0.py to help in debugging updated the 'doc' section -- needs publishing added direct conversion of Class Based Design modules - resulting in lesss boiler-plate code
58 lines
1.7 KiB
Python
58 lines
1.7 KiB
Python
import myhdl
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from myhdl import *
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ACTIVE = 0
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DirType = enum('RIGHT', 'LEFT')
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def jc2(goLeft, goRight, stop, clk, q):
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""" A bi-directional 4-bit Johnson counter with stop control.
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I/O pins:
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--------
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clk : input free-running slow clock
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goLeft : input signal to shift left (active-low switch)
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goRight : input signal to shift right (active-low switch)
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stop : input signal to stop counting (active-low switch)
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q : 4-bit counter output (active-low LEDs; q[0] is right-most)
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Operation:
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---------
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The counter is triggered on the rising edge of the clock (clk).
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A low pulse on the goLeft input will cause the counter to start
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shifting left from its current state. A low pulse on the goRight
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input will cause the counter to start shifting right from its
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current state. A low pulse on the stop input will cause the
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counter to hold its current state until goLeft or goRight is pulsed.
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After power-up, the counter is stopped with all outputs low (LEDs lit).
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"""
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dir = Signal(DirType.LEFT)
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run = Signal(False)
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@always(clk.posedge)
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def synch():
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# direction
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if goRight == ACTIVE:
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dir.next = DirType.RIGHT
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run.next = True
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elif goLeft == ACTIVE:
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dir.next = DirType.LEFT
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run.next = True
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# stop
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if stop == ACTIVE:
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run.next = False
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# counter action
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if run:
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if dir == DirType.LEFT:
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q.next[4:1] = q[3:]
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q.next[0] = not q[3]
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else:
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q.next[3:] = q[4:1]
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q.next[3] = not q[0]
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return synch
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