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16 lines
256 B
Python
16 lines
256 B
Python
from myhdl import Signal, intbv
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from bin2gray import bin2gray
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def convert(hdl, width=8):
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B = Signal(intbv(0)[width:])
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G = Signal(intbv(0)[width:])
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inst = bin2gray(B, G)
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inst.convert(hdl=hdl)
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convert(hdl='Verilog')
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convert(hdl='VHDL')
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