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* 1) added J. Villars code from PR#238 (https://github.com/myhdl/myhdl/pull/328) to augment the `@block` decorator with arguments, initially to keep the generated names simpler especially when nesting `block`s without adding *hdl* code - I modified it a bit using `skipname=False` rather than `keepname=True` as default 2) added _hdlclass.py to support Class Based Design, look at bot test/conversion/general/test_hdlclass.py and test/conversion/general/test_hdlclass2.py This needed the changes of 1) above. * 1) _Signal.py added property `.nbits` for use in HDL iso `len(sig)`, anticipating Structure and Array where `len()` is not what `.nbits` will give you ... added `duplicate(value=None)` method to avoid that ugly `newsig = Signal(oldsig._val)` 2) _block.py minor changes 3)_hdlclass.py removed ForwardPorts resolution as this currently adds a *stray* sig in the .vcd output - even if noe ForwardPorts are present cleaned the code to what is actually working 4) _traceSignals.py The `@block(skipname=True), which is heavily used in Class Based Design, applies `None` as that block-name and this will show up as an additional level in the .vcd which looks ugly and distracting. So reworked this file to skip adding the None-level Also added indents in the .vcd var section, primarily for debugging, but kept this as it looks nice. Introduce f'strings 5) _analyze.py changed UPPER_CASE naming of processe/always into lower case, making the generated signals conform with the producing process/always 6) test_xxxx.py changed @instance with *logic* as function name into *comb* as `logic` has become a reserved Verilog keyword * cleaned test/bugs replacing generator names *logic* and *output* with *comb* as `logic` and `output` have become Verilog reserved keywords * replacing more occurrences of *logic* by either *comb* or *synch* * one *comb* too many :( * added small test_hdlclass0.py to help in debugging updated the 'doc' section -- needs publishing added direct conversion of Class Based Design modules - resulting in lesss boiler-plate code
52 lines
1.1 KiB
Python
52 lines
1.1 KiB
Python
import myhdl
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from myhdl import *
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from random import randrange
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def arbiter(grant_vector, request_vector):
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@always_comb
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def comb():
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grant_vector.next = 0
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for i in range(len(request_vector)):
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if request_vector[i] == 1:
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grant_vector.next[i] = 1
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break
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return comb
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def check():
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M = 8
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request_list = [Signal(bool()) for i in range(M)]
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request_vector = ConcatSignal(*reversed(request_list))
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grant_vector = Signal(intbv(0)[M:])
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grant_list = [grant_vector(i) for i in range(M)]
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arb = arbiter(grant_vector, request_vector)
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@instance
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def stimulus():
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for i in range(100):
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for j in range(M):
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request_list[j].next = randrange(2)
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yield delay(10)
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if 1 in request_list:
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assert grant_list.index(1) == request_list.index(1)
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assert grant_list.count(0) == M - 1
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# print bin(grant_vector, 8), bin(request_vector, 8)
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raise StopSimulation()
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return arb, stimulus
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sim = Simulation(check())
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sim.run()
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