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https://github.com/myhdl/myhdl.git
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90 lines
2.3 KiB
Python
90 lines
2.3 KiB
Python
import myhdl
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from myhdl import *
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def long_divider(
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quotient,
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ready,
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dividend,
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divisor,
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start,
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clock,
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reset
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):
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M = len(dividend)
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N = len(divisor)
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Q = len(quotient)
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assert M-N == Q
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st = enum("WAIT_START", "CALC")
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@instance
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def proc():
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state = st.WAIT_START
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div = intbv(0)[N+1:]
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divbits = intbv(0)[Q-1:]
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quot = intbv(0)[Q:]
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count = intbv(0, min=0, max=Q)
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while True:
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yield clock.posedge, reset.posedge
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if reset == 1:
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quotient.next = 0
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ready.next = 0
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state = st.WAIT_START
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div[:] = 0
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divbits[:] = 0
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quot[:] = 0
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else:
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if state == st.WAIT_START:
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if start:
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state = st.CALC
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ready.next = 0
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quot[:] = 0
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div[N+1:] = dividend[M:Q-1]
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divbits[:] = dividend[Q-1:]
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count[:] = 0
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elif state == st.CALC:
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quot[Q:1] = quot[Q-1:]
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if div >= divisor:
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quot[0] = 1
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div -= divisor
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else:
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quot[0] = 0
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if count == Q-1:
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ready.next = 1
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state = st.WAIT_START
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else:
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div[N+1:1] = div[N:]
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div[0] = divbits[Q-2]
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divbits[Q-1:1] = divbits[Q-2:]
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count += 1
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quotient.next = quot
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return proc
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if __name__ == '__main__':
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quotient = Signal(intbv(0)[22:])
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ready = Signal(bool())
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dividend = Signal(intbv(0)[38:])
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divisor = Signal(intbv(0)[16:])
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start = Signal(bool())
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clock = Signal(bool())
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reset = Signal(bool())
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toVHDL(long_divider,
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quotient,
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ready,
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dividend,
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divisor,
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start,
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clock,
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reset
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)
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