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84 lines
2.0 KiB
Python
84 lines
2.0 KiB
Python
import myhdl
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from myhdl import *
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from glibc_random import glibc_random
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from long_divider import long_divider
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def test_longdiv(nrvectors=2**18):
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quotient = Signal(intbv(0)[22:])
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ready = Signal(bool())
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dividend = Signal(intbv(0)[38:])
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divisor = Signal(intbv(0)[16:])
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start = Signal(bool())
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clock = Signal(bool())
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reset = Signal(bool())
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stopped = Signal(bool())
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MAXVAL = 2**22 - 1
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dut = long_divider(
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quotient,
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ready,
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dividend,
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divisor,
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start,
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clock,
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reset
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)
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@instance
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def clockgen():
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clock.next = 0
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yield delay(10)
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while not stopped:
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clock.next = not clock
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yield delay(10)
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@instance
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def stimulus():
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stopped.next = 0
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yield delay(10)
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random_word = intbv(0)[32:]
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p = intbv(0)[16:]
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q = intbv(0)[22:]
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d = intbv(0)[38:]
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yield clock.negedge
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reset.next = 0
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yield clock.negedge
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reset.next = 1
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yield clock.negedge
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reset.next = 0
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start.next = 0
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yield clock.negedge
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random_word[:] = 94
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for i in range(nrvectors):
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yield clock.negedge
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random_word[:] = glibc_random(random_word)
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p[:] = random_word[16:]
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random_word[:] = glibc_random(random_word)
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q[:] = random_word[22:]
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if p == 0:
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q[:] = MAXVAL
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d[:] = p * q
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dividend.next = d
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divisor.next = p
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start.next = 1
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yield clock.negedge
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start.next = 0
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yield ready.posedge
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"""compensate for Verilog's non-determinism"""
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yield delay(1)
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#print d, p, q, quotient
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assert quotient == q
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stopped.next = 1
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yield delay(10)
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#raise StopSimulation()
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return dut, clockgen, stimulus
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if __name__ == '__main__':
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sim = Simulation(test_longdiv())
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sim.run()
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