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66 lines
1.6 KiB
Python
66 lines
1.6 KiB
Python
import myhdl
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from myhdl import *
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from timer import timer_sig, timer_var
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def test_timer_array(timer):
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MAXVAL = 1234
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clock = Signal(bool())
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reset = Signal(bool())
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flag0 = Signal(bool())
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flag1 = Signal(bool())
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flag2 = Signal(bool())
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flag3= Signal(bool())
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flag4 = Signal(bool())
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flag5 = Signal(bool())
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flag6 = Signal(bool())
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flag7 = Signal(bool())
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dut = [None] * 8
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dut[0] = timer(flag0, clock, reset, MAXVAL)
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dut[1] = timer(flag1, clock, reset, MAXVAL)
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dut[2] = timer(flag2, clock, reset, MAXVAL)
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dut[3] = timer(flag3, clock, reset, MAXVAL)
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dut[4] = timer(flag4, clock, reset, MAXVAL)
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dut[5] = timer(flag5, clock, reset, MAXVAL)
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dut[6] = timer(flag6, clock, reset, MAXVAL)
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dut[7] = timer(flag7, clock, reset, MAXVAL)
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@instance
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def clkgen():
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clock.next = 0
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reset.next = 0
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yield delay(10)
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reset.next = 1
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yield delay(10)
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reset.next = 0
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yield delay(10)
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for i in range(2**24):
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clock.next = not clock
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yield delay(10)
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@instance
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def monitor():
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count = intbv(0, min=0, max=MAXVAL+1)
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seen = False
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while True:
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yield clock.posedge
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if seen:
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if flag0:
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assert count == MAXVAL
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else:
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count += 1
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if flag0 or flag1 or flag2 or flag3 or flag4 or flag5 or flag6 or flag7:
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seen = True
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count[:] = 0
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return dut, clkgen, monitor
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if __name__ == '__main__':
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sim = Simulation(test_timer_array(timer_var))
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sim.run()
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