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* 1) added J. Villars code from PR#238 (https://github.com/myhdl/myhdl/pull/328) to augment the `@block` decorator with arguments, initially to keep the generated names simpler especially when nesting `block`s without adding *hdl* code - I modified it a bit using `skipname=False` rather than `keepname=True` as default 2) added _hdlclass.py to support Class Based Design, look at bot test/conversion/general/test_hdlclass.py and test/conversion/general/test_hdlclass2.py This needed the changes of 1) above. * 1) _Signal.py added property `.nbits` for use in HDL iso `len(sig)`, anticipating Structure and Array where `len()` is not what `.nbits` will give you ... added `duplicate(value=None)` method to avoid that ugly `newsig = Signal(oldsig._val)` 2) _block.py minor changes 3)_hdlclass.py removed ForwardPorts resolution as this currently adds a *stray* sig in the .vcd output - even if noe ForwardPorts are present cleaned the code to what is actually working 4) _traceSignals.py The `@block(skipname=True), which is heavily used in Class Based Design, applies `None` as that block-name and this will show up as an additional level in the .vcd which looks ugly and distracting. So reworked this file to skip adding the None-level Also added indents in the .vcd var section, primarily for debugging, but kept this as it looks nice. Introduce f'strings 5) _analyze.py changed UPPER_CASE naming of processe/always into lower case, making the generated signals conform with the producing process/always 6) test_xxxx.py changed @instance with *logic* as function name into *comb* as `logic` has become a reserved Verilog keyword * cleaned test/bugs replacing generator names *logic* and *output* with *comb* as `logic` and `output` have become Verilog reserved keywords * replacing more occurrences of *logic* by either *comb* or *synch* * one *comb* too many :( * added small test_hdlclass0.py to help in debugging updated the 'doc' section -- needs publishing added direct conversion of Class Based Design modules - resulting in lesss boiler-plate code
43 lines
919 B
Python
43 lines
919 B
Python
import myhdl
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from myhdl import *
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def timer_sig(flag, clock, reset, MAXVAL):
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count = Signal(intbv(0, min=0, max=MAXVAL + 1))
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@always (clock.posedge, reset.posedge)
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def synch():
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if reset == 1:
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count.next = 0
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else:
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flag.next = 0
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if count == MAXVAL:
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flag.next = 1
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count.next = 0
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else:
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count.next = count + 1
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return synch
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def timer_var(flag, clock, reset, MAXVAL):
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@instance
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def comb():
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count = intbv(0, min=0, max=MAXVAL + 1)
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while True:
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yield clock.posedge, reset.posedge
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if reset == 1:
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count[:] = 0
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else:
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flag.next = 0
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if count == MAXVAL:
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flag.next = 1
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count[:] = 0
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else:
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count += 1
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return comb
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