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64 lines
1.4 KiB
VHDL
64 lines
1.4 KiB
VHDL
-- File: GrayIncReg.vhd
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-- Generated by MyHDL 0.8dev
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-- Date: Fri Dec 21 15:02:38 2012
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library IEEE;
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use IEEE.std_logic_1164.all;
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use IEEE.numeric_std.all;
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use std.textio.all;
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use work.pck_myhdl_08.all;
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entity GrayIncReg is
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port (
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graycnt: out unsigned(7 downto 0);
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enable: in std_logic;
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clock: in std_logic;
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reset: in std_logic
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);
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end entity GrayIncReg;
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architecture MyHDL of GrayIncReg is
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signal graycnt_comb: unsigned(7 downto 0);
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signal gray_inc_1_bincnt: unsigned(7 downto 0);
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begin
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GRAYINCREG_GRAY_INC_1_INC_1_INCLOGIC: process (clock, reset) is
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begin
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if (reset = '0') then
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gray_inc_1_bincnt <= (others => '0');
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elsif rising_edge(clock) then
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if bool(enable) then
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gray_inc_1_bincnt <= (gray_inc_1_bincnt + 1);
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end if;
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end if;
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end process GRAYINCREG_GRAY_INC_1_INC_1_INCLOGIC;
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GRAYINCREG_GRAY_INC_1_BIN2GRAY_1_LOGIC: process (gray_inc_1_bincnt) is
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variable Bext: unsigned(8 downto 0);
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begin
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Bext := to_unsigned(0, 9);
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Bext := resize(gray_inc_1_bincnt, 9);
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for i in 0 to 8-1 loop
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graycnt_comb(i) <= (Bext((i + 1)) xor Bext(i));
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end loop;
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end process GRAYINCREG_GRAY_INC_1_BIN2GRAY_1_LOGIC;
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GRAYINCREG_REG_1: process (clock) is
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begin
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if rising_edge(clock) then
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graycnt <= graycnt_comb;
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end if;
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end process GRAYINCREG_REG_1;
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end architecture MyHDL;
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