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938 lines
21 KiB
ReStructuredText
938 lines
21 KiB
ReStructuredText
.. currentmodule:: myhdl
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.. _conv-usage:
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*******************
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Conversion examples
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*******************
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.. _conv-usage-intro:
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Introduction
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============
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In this chapter, we will demonstrate the conversion process with a
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number of examples. For the concepts of MyHDL conversion,
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read the companion chapter :ref:`conv`.
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.. _conv-usage-seq:
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A small sequential design
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=========================
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Consider the following MyHDL code for an incrementer module::
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ACTIVE_LOW, INACTIVE_HIGH = 0, 1
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def Inc(count, enable, clock, reset, n):
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""" Incrementer with enable.
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count -- output
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enable -- control input, increment when 1
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clock -- clock input
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reset -- asynchronous reset input
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n -- counter max value
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"""
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@always(clock.posedge, reset.negedge)
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def incLogic():
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if reset == ACTIVE_LOW:
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count.next = 0
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else:
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if enable:
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count.next = (count + 1) % n
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return incLogic
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In Verilog terminology, function :func:`inc` corresponds to a module, while the
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decorated function :func:`incLogic` roughly corresponds to an always block.
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Normally, to simulate the design, we would elaborate an instance as follows::
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m = 8
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n = 2 ** m
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count = Signal(intbv(0)[m:])
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enable = Signal(bool(0))
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clock, reset = [Signal(bool()) for i in range(2)]
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inc_inst = Inc(count, enable, clock, reset, n=n)
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``inc_inst`` is an elaborated design instance that can be simulated. To convert
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it to Verilog, we change the last line as follows::
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inc_inst = toVerilog(Inc, count, enable, clock, reset, n=n)
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Again, this creates an instance that can be simulated, but as a side effect, it
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also generates an equivalent Verilog module in file :file:`Inc.v`. The Verilog
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code looks as follows::
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module Inc (
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count,
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enable,
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clock,
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reset
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);
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output [7:0] count;
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reg [7:0] count;
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input enable;
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input clock;
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input reset;
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always @(posedge clock, negedge reset) begin: INC_INCLOGIC
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if ((reset == 0)) begin
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count <= 0;
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end
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else begin
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if (enable) begin
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count <= ((count + 1) % 256);
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end
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end
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end
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endmodule
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Similarly, we can convert to VHDL as follows::
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inc_inst = toVHDL(Inc, count, enable, clock, reset, n=n)
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This creates an equivalent VHDL module in file :file:`Inc.vhd`::
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library IEEE;
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use IEEE.std_logic_1164.all;
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use IEEE.numeric_std.all;
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use work.pck_myhdl_06.all;
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entity Inc is
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port (
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count: inout unsigned(7 downto 0);
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enable: in std_logic;
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clock: in std_logic;
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reset: in std_logic
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);
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end entity Inc;
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architecture MyHDL of Inc is
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begin
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INC_INCLOGIC: process (clock, reset) is
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begin
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if (reset = '0') then
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count <= "00000000";
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elsif rising_edge(clock) then
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if to_boolean(enable) then
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count <= ((count + 1) mod 256);
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end if;
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end if;
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end process INC_INCLOGIC;
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end architecture MyHDL;
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.. _conv-usage-comb:
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A small combinatorial design
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============================
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The second example is a small combinatorial design, more specifically the binary
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to Gray code converter from previous chapters::
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def bin2gray(B, G, width):
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""" Gray encoder.
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B -- input intbv signal, binary encoded
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G -- output intbv signal, gray encoded
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width -- bit width
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"""
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@always_comb
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def logic():
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Bext = intbv(0)[width+1:]
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Bext[:] = B
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for i in range(width):
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G.next[i] = Bext[i+1] ^ Bext[i]
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return logic
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As before, you can create an instance and convert to Verilog and VHDL as follows::
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width = 8
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B = Signal(intbv(0)[width:])
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G = Signal(intbv(0)[width:])
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bin2gray_inst = toVerilog(bin2gray, B, G, width)
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bin2gray_inst = toVHDL(bin2gray, B, G, width)
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The generated Verilog code looks as follows::
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module bin2gray (
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B,
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G
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);
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input [7:0] B;
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output [7:0] G;
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reg [7:0] G;
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always @(B) begin: BIN2GRAY_LOGIC
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integer i;
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reg [9-1:0] Bext;
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Bext = 9'h0;
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Bext = B;
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for (i=0; i<8; i=i+1) begin
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G[i] <= (Bext[(i + 1)] ^ Bext[i]);
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end
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end
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endmodule
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The generated VHDL code looks as follows::
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library IEEE;
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use IEEE.std_logic_1164.all;
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use IEEE.numeric_std.all;
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use std.textio.all;
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use work.pck_myhdl_06.all;
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entity bin2gray is
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port (
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B: in unsigned(7 downto 0);
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G: out unsigned(7 downto 0)
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);
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end entity bin2gray;
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architecture MyHDL of bin2gray is
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begin
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BIN2GRAY_LOGIC: process (B) is
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variable Bext: unsigned(8 downto 0);
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begin
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Bext := to_unsigned(0, 9);
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Bext := resize(B, 9);
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for i in 0 to 8-1 loop
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G(i) <= (Bext((i + 1)) xor Bext(i));
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end loop;
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end process BIN2GRAY_LOGIC;
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end architecture MyHDL;
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.. _conv-usage-hier:
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A hierarchical design
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=====================
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The converter can handle designs with an arbitrarily deep hierarchy.
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For example, suppose we want to design an incrementer with Gray code output.
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Using the designs from previous sections, we can proceed as follows::
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def GrayInc(graycnt, enable, clock, reset, width):
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bincnt = Signal(intbv(0)[width:])
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inc_1 = inc(bincnt, enable, clock, reset, n=2**width)
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bin2gray_1 = bin2gray(B=bincnt, G=graycnt, width=width)
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return inc_1, bin2gray_1
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According to Gray code properties, only a single bit will change in consecutive
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values. However, as the ``bin2gray`` module is combinatorial, the output bits
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may have transient glitches, which may not be desirable. To solve this, let's
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create an additional level of hierarchy and add an output register to the
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design. (This will create an additional latency of a clock cycle, which may not
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be acceptable, but we will ignore that here.) ::
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def GrayIncReg(graycnt, enable, clock, reset, width):
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graycnt_comb = Signal(intbv(0)[width:])
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gray_inc_1 = GrayInc(graycnt_comb, enable, clock, reset, width)
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@always(clock.posedge)
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def reg_1():
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graycnt.next = graycnt_comb
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return gray_inc_1, reg_1
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We can convert this hierarchical design as before::
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width = 8
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graycnt = Signal(intbv()[width:])
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enable, clock, reset = [Signal(bool()) for i in range(3)]
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toVerilog(GrayIncReg, graycnt, enable, clock, reset, width)
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toVHDL(GrayIncReg, graycnt, enable, clock, reset, width)
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The Verilog output code looks as follows::
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module GrayIncReg (
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graycnt,
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enable,
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clock,
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reset
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);
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output [7:0] graycnt;
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reg [7:0] graycnt;
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input enable;
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input clock;
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input reset;
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reg [7:0] graycnt_comb;
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reg [7:0] gray_inc_1_bincnt;
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always @(posedge clock, negedge reset) begin: GRAYINCREG_GRAY_INC_1_INC_1_INCLOGIC
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if ((reset == 0)) begin
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gray_inc_1_bincnt <= 0;
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end
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else begin
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if (enable) begin
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gray_inc_1_bincnt <= ((gray_inc_1_bincnt + 1) % 256);
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end
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end
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end
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always @(gray_inc_1_bincnt) begin: GRAYINCREG_GRAY_INC_1_BIN2GRAY_1_LOGIC
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integer i;
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reg [9-1:0] Bext;
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Bext = 9'h0;
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Bext = gray_inc_1_bincnt;
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for (i=0; i<8; i=i+1) begin
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graycnt_comb[i] <= (Bext[(i + 1)] ^ Bext[i]);
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end
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end
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always @(posedge clock) begin: GRAYINCREG_REG_1
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graycnt <= graycnt_comb;
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end
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endmodule
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The VHDL output code looks as follows::
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library IEEE;
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use IEEE.std_logic_1164.all;
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use IEEE.numeric_std.all;
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use work.pck_myhdl_06.all;
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entity GrayIncReg is
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port (
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graycnt: out unsigned(7 downto 0);
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enable: in std_logic;
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clock: in std_logic;
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reset: in std_logic
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);
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end entity GrayIncReg;
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architecture MyHDL of GrayIncReg is
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signal graycnt_comb: unsigned(7 downto 0);
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signal gray_inc_1_bincnt: unsigned(7 downto 0);
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begin
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GRAYINCREG_GRAY_INC_1_INC_1_INCLOGIC: process (clock, reset) is
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begin
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if (reset = '0') then
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gray_inc_1_bincnt <= "00000000";
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elsif rising_edge(clock) then
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if to_boolean(enable) then
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gray_inc_1_bincnt <= ((gray_inc_1_bincnt + 1) mod 256);
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end if;
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end if;
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end process GRAYINCREG_GRAY_INC_1_INC_1_INCLOGIC;
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GRAYINCREG_GRAY_INC_1_BIN2GRAY_1_LOGIC: process (gray_inc_1_bincnt) is
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variable Bext: unsigned(8 downto 0);
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begin
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Bext := to_unsigned(0, 9);
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Bext := resize(gray_inc_1_bincnt, 9);
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for i in 0 to 8-1 loop
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graycnt_comb(i) <= (Bext((i + 1)) xor Bext(i));
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end loop;
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end process GRAYINCREG_GRAY_INC_1_BIN2GRAY_1_LOGIC;
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GRAYINCREG_REG_1: process (clock) is
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begin
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if rising_edge(clock) then
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graycnt <= graycnt_comb;
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end if;
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end process GRAYINCREG_REG_1;
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end architecture MyHDL;
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Note that the output is a flat "net list of blocks", and that hierarchical
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signal names are generated as necessary.
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.. _conv-usage-fsm:
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Optimizations for finite state machines
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=======================================
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As often in hardware design, finite state machines deserve special attention.
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In Verilog and VHDL, finite state machines are typically described using case
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statements. Python doesn't have a case statement, but the converter recognizes
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particular if-then-else structures and maps them to case statements. This
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optimization occurs when a variable whose type is an enumerated type is
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sequentially tested against enumeration items in an if-then-else structure.
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Also, the appropriate synthesis pragmas for efficient synthesis are generated in
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the Verilog code.
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As a further optimization, function :func:`enum` was enhanced to support
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alternative encoding schemes elegantly, using an additional parameter
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*encoding*. For example::
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t_State = enum('SEARCH', 'CONFIRM', 'SYNC', encoding='one_hot')
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The default encoding is ``'binary'``; the other possibilities are ``'one_hot'``
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and ``'one_cold'``. This parameter only affects the conversion output, not the
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behavior of the type. The generated Verilog code for case statements is
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optimized for an efficient implementation according to the encoding. Note that
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in contrast, a Verilog designer has to make nontrivial code changes to implement
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a different encoding scheme.
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As an example, consider the following finite state machine, whose state variable
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uses the enumeration type defined above::
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ACTIVE_LOW = bool(0)
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FRAME_SIZE = 8
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t_State = enum('SEARCH', 'CONFIRM', 'SYNC', encoding="one_hot")
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def FramerCtrl(SOF, state, syncFlag, clk, reset_n):
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""" Framing control FSM.
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SOF -- start-of-frame output bit
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state -- FramerState output
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syncFlag -- sync pattern found indication input
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clk -- clock input
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reset_n -- active low reset
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"""
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index = Signal(intbv(0)[8:]) # position in frame
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@always(clk.posedge, reset_n.negedge)
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def FSM():
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if reset_n == ACTIVE_LOW:
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SOF.next = 0
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index.next = 0
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state.next = t_State.SEARCH
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else:
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index.next = (index + 1) % FRAME_SIZE
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SOF.next = 0
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if state == t_State.SEARCH:
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index.next = 1
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if syncFlag:
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state.next = t_State.CONFIRM
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elif state == t_State.CONFIRM:
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if index == 0:
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if syncFlag:
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state.next = t_State.SYNC
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else:
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state.next = t_State.SEARCH
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elif state == t_State.SYNC:
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if index == 0:
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if not syncFlag:
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state.next = t_State.SEARCH
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SOF.next = (index == FRAME_SIZE-1)
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else:
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raise ValueError("Undefined state")
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return FSM
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The conversion is done as before::
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SOF = Signal(bool(0))
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syncFlag = Signal(bool(0))
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clk = Signal(bool(0))
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reset_n = Signal(bool(1))
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state = Signal(t_State.SEARCH)
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toVerilog(FramerCtrl, SOF, state, syncFlag, clk, reset_n)
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toVHDL(FramerCtrl, SOF, state, syncFlag, clk, reset_n)
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The Verilog output looks as follows::
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module FramerCtrl (
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SOF,
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state,
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syncFlag,
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clk,
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reset_n
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);
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output SOF;
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reg SOF;
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output [2:0] state;
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reg [2:0] state;
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input syncFlag;
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input clk;
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input reset_n;
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reg [7:0] index;
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always @(posedge clk, negedge reset_n) begin: FRAMERCTRL_FSM
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if ((reset_n == 0)) begin
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SOF <= 0;
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index <= 0;
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state <= 3'b001;
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end
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else begin
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index <= ((index + 1) % 8);
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SOF <= 0;
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// synthesis parallel_case full_case
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casez (state)
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3'b??1: begin
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index <= 1;
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if (syncFlag) begin
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state <= 3'b010;
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end
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end
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3'b?1?: begin
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if ((index == 0)) begin
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if (syncFlag) begin
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state <= 3'b100;
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end
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else begin
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state <= 3'b001;
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end
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end
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end
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3'b1??: begin
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if ((index == 0)) begin
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if ((!syncFlag)) begin
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state <= 3'b001;
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end
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end
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SOF <= (index == (8 - 1));
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end
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default: begin
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$finish;
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end
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endcase
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end
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end
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endmodule
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The VHDL output looks as follows::
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package pck_FramerCtrl is
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type t_enum_t_State_1 is (
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SEARCH,
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CONFIRM,
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SYNC
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);
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attribute enum_encoding of t_enum_t_State_1: type is "001 010 100";
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end package pck_FramerCtrl;
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library IEEE;
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use IEEE.std_logic_1164.all;
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use IEEE.numeric_std.all;
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use std.textio.all;
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use work.pck_myhdl_06.all;
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use work.pck_FramerCtrl.all;
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entity FramerCtrl is
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port (
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SOF: out std_logic;
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state: inout t_enum_t_State_1;
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syncFlag: in std_logic;
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clk: in std_logic;
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reset_n: in std_logic
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);
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end entity FramerCtrl;
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architecture MyHDL of FramerCtrl is
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signal index: unsigned(7 downto 0);
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begin
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FRAMERCTRL_FSM: process (clk, reset_n) is
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begin
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if (reset_n = '0') then
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SOF <= '0';
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index <= "00000000";
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state <= SEARCH;
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elsif rising_edge(clk) then
|
|
index <= ((index + 1) mod 8);
|
|
SOF <= '0';
|
|
case state is
|
|
when SEARCH =>
|
|
index <= "00000001";
|
|
if to_boolean(syncFlag) then
|
|
state <= CONFIRM;
|
|
end if;
|
|
when CONFIRM =>
|
|
if (index = 0) then
|
|
if to_boolean(syncFlag) then
|
|
state <= SYNC;
|
|
else
|
|
state <= SEARCH;
|
|
end if;
|
|
end if;
|
|
when SYNC =>
|
|
if (index = 0) then
|
|
if (not to_boolean(syncFlag)) then
|
|
state <= SEARCH;
|
|
end if;
|
|
end if;
|
|
SOF <= to_std_logic(signed(resize(index, 9)) = (8 - 1));
|
|
when others =>
|
|
assert False report "End of Simulation" severity Failure;
|
|
end case;
|
|
end if;
|
|
end process FRAMERCTRL_FSM;
|
|
|
|
end architecture MyHDL;
|
|
|
|
|
|
.. _conf-usage-ram:
|
|
|
|
RAM inference
|
|
=============
|
|
|
|
Certain synthesis tools can map Verilog memories to RAM structures. To support
|
|
this interesting feature, the Verilog converter maps lists of signals in MyHDL
|
|
to Verilog memories.
|
|
|
|
The following MyHDL example is a ram model that uses a list of signals to model
|
|
the internal memory. ::
|
|
|
|
def RAM(dout, din, addr, we, clk, depth=128):
|
|
""" Ram model """
|
|
|
|
mem = [Signal(intbv(0)[8:]) for i in range(depth)]
|
|
|
|
@always(clk.posedge)
|
|
def write():
|
|
if we:
|
|
mem[int(addr)].next = din
|
|
|
|
@always_comb
|
|
def read():
|
|
dout.next = mem[int(addr)]
|
|
|
|
return write, read
|
|
|
|
With the appropriate signal definitions for the interface ports, it is converted
|
|
to the following Verilog code. Note how the list of signals ``mem`` is mapped to
|
|
a Verilog memory. ::
|
|
|
|
module ram (
|
|
dout,
|
|
din,
|
|
addr,
|
|
we,
|
|
clk
|
|
);
|
|
|
|
output [7:0] dout;
|
|
wire [7:0] dout;
|
|
input [7:0] din;
|
|
input [6:0] addr;
|
|
input we;
|
|
input clk;
|
|
|
|
|
|
reg [7:0] mem [0:128-1];
|
|
|
|
|
|
always @(posedge clk) begin: RAM_1_WRITE
|
|
if (we) begin
|
|
mem[addr] <= din;
|
|
end
|
|
end
|
|
|
|
|
|
assign dout = mem[addr];
|
|
|
|
endmodule
|
|
|
|
In VHDL, the list of MyHDL signals is modeled as a VHDL array signal::
|
|
|
|
library IEEE;
|
|
use IEEE.std_logic_1164.all;
|
|
use IEEE.numeric_std.all;
|
|
|
|
use work.pck_myhdl_06.all;
|
|
|
|
entity ram is
|
|
port (
|
|
dout: out unsigned(7 downto 0);
|
|
din: in unsigned(7 downto 0);
|
|
addr: in unsigned(6 downto 0);
|
|
we: in std_logic;
|
|
clk: in std_logic
|
|
);
|
|
end entity ram;
|
|
|
|
architecture MyHDL of ram is
|
|
|
|
type t_array_mem is array(0 to 128-1) of unsigned(7 downto 0);
|
|
signal mem: t_array_mem;
|
|
|
|
begin
|
|
|
|
RAM_WRITE: process (clk) is
|
|
begin
|
|
if rising_edge(clk) then
|
|
if to_boolean(we) then
|
|
mem(to_integer(addr)) <= din;
|
|
end if;
|
|
end if;
|
|
end process RAM_WRITE;
|
|
|
|
|
|
dout <= mem(to_integer(addr));
|
|
|
|
end architecture MyHDL;
|
|
|
|
|
|
|
|
.. _conf-usage-rom:
|
|
|
|
ROM inference
|
|
=============
|
|
|
|
Some synthesis tools can infer a ROM memory from a case statement. The Verilog
|
|
converter can perform the expansion into a case statement automatically, based
|
|
on a higher level description. The ROM access is described in a single line, by
|
|
indexing into a tuple of integers. The tuple can be described manually, but also
|
|
by programmatical means. Note that a tuple is used instead of a list to stress
|
|
the read-only character of the memory.
|
|
|
|
The following example illustrates this functionality. ROM access is described as
|
|
follows::
|
|
|
|
def rom(dout, addr, CONTENT):
|
|
|
|
@always_comb
|
|
def read():
|
|
dout.next = CONTENT[int(addr)]
|
|
|
|
return read
|
|
|
|
The ROM content is described as a tuple of integers. When the ROM content is
|
|
defined, the conversion can be performed::
|
|
|
|
CONTENT = (17, 134, 52, 9)
|
|
dout = Signal(intbv(0)[8:])
|
|
addr = Signal(intbv(0)[4:])
|
|
|
|
toVerilog(rom, dout, addr, CONTENT)
|
|
toVHDL(rom, dout, addr, CONTENT)
|
|
|
|
The Verilog output code is as follows::
|
|
|
|
module rom (
|
|
dout,
|
|
addr
|
|
);
|
|
|
|
output [7:0] dout;
|
|
reg [7:0] dout;
|
|
input [3:0] addr;
|
|
|
|
|
|
|
|
|
|
always @(addr) begin: ROM_READ
|
|
// synthesis parallel_case full_case
|
|
case (addr)
|
|
0: dout <= 17;
|
|
1: dout <= 134;
|
|
2: dout <= 52;
|
|
default: dout <= 9;
|
|
endcase
|
|
end
|
|
|
|
endmodule
|
|
|
|
|
|
The VHDL output code is as follows::
|
|
|
|
|
|
library IEEE;
|
|
use IEEE.std_logic_1164.all;
|
|
use IEEE.numeric_std.all;
|
|
use std.textio.all;
|
|
|
|
use work.pck_myhdl_06.all;
|
|
|
|
entity rom is
|
|
port (
|
|
dout: out unsigned(7 downto 0);
|
|
addr: in unsigned(3 downto 0)
|
|
);
|
|
end entity rom;
|
|
|
|
architecture MyHDL of rom is
|
|
|
|
|
|
begin
|
|
|
|
|
|
ROM_READ: process (addr) is
|
|
begin
|
|
case to_integer(addr) is
|
|
when 0 => dout <= "00010001";
|
|
when 1 => dout <= "10000110";
|
|
when 2 => dout <= "00110100";
|
|
when others => dout <= "00001001";
|
|
end case;
|
|
end process ROM_READ;
|
|
|
|
end architecture MyHDL;
|
|
|
|
|
|
.. _conf-usage-custom:
|
|
|
|
User-defined code
|
|
=================
|
|
|
|
MyHDL provides a way to include user-defined code during the
|
|
conversion process.
|
|
|
|
MyHDL defines hooks that are understood by the converter but ignored
|
|
by the simulator. The hooks are ``__verilog__`` for Verilog and
|
|
``__vhdl__`` for VHDL. They operate like a special return value. When
|
|
defined in a MyHDL function. the convertor will use its value instead
|
|
of the regular return value.
|
|
|
|
The value of ``__verilog__`` or ``__vhdl__`` should be a format string
|
|
that uses keys in its format specifiers. The keys refer to the
|
|
variable names in the context of the string.
|
|
|
|
For example::
|
|
|
|
def inc_comb(nextCount, count, n):
|
|
|
|
@always(count)
|
|
def logic():
|
|
# do nothing here
|
|
pass
|
|
|
|
nextCount.driven = "wire"
|
|
|
|
__verilog__ =\
|
|
"""
|
|
assign %(nextCount)s = (%(count)s + 1) %% %(n)s;
|
|
"""
|
|
|
|
__vhdl__ =\
|
|
"""
|
|
%(nextCount)s <= (%(count)s + 1) mod %(n)s;
|
|
"""
|
|
|
|
return logic
|
|
|
|
The converted code looks as follows in Verilog::
|
|
|
|
module inc_comb (
|
|
nextCount,
|
|
count
|
|
);
|
|
|
|
output [7:0] nextCount;
|
|
wire [7:0] nextCount;
|
|
input [7:0] count;
|
|
|
|
assign nextCount = (count + 1) % 256;
|
|
|
|
endmodule
|
|
|
|
and as follows in VHDL::
|
|
|
|
library IEEE;
|
|
use IEEE.std_logic_1164.all;
|
|
use IEEE.numeric_std.all;
|
|
|
|
use work.pck_myhdl_06.all;
|
|
|
|
entity inc_comb is
|
|
port (
|
|
nextCount: out unsigned(7 downto 0);
|
|
count: in unsigned(7 downto 0)
|
|
);
|
|
end entity inc_comb;
|
|
|
|
architecture MyHDL of inc_comb is
|
|
|
|
begin
|
|
|
|
nextCount <= (count + 1) mod 256;
|
|
|
|
end architecture MyHDL;
|
|
|
|
|
|
In this example, conversion of the :func:`inc_comb` function is
|
|
bypassed and the user-defined code is inserted instead. Note that the
|
|
user-defined code refers to signals and parameters in the MyHDL
|
|
context by using format specifiers. During conversion, the appropriate
|
|
hierarchical names and parameter values will be filled in. Note also
|
|
that the format specifier indicator % needs to be escaped (by doubling
|
|
it) if it is required in the user-defined code.
|
|
|
|
There is one more issue that needs user attention for the Verilog
|
|
case. Normally, the Verilog converter infers inputs, internal signals,
|
|
and outputs. It also detects undriven and multiple driven signals. To
|
|
do this, it assumes that signals are not driven by default. It then
|
|
processes the code to find out which signals are driven from
|
|
where. However, it cannot do this for user-defined code. Without
|
|
additional help, this will result in warnings or errors during the
|
|
inference process, or in compilation errors from invalid Verilog
|
|
code. The user should solve this by setting the ``driven`` attribute
|
|
for signals that are driven from the user- defined code. In the
|
|
example code above, note the following assignment::
|
|
|
|
nextCount.driven = "wire"
|
|
|
|
This specifies that the nextCount signal is driven as a Verilog wire from this
|
|
module. The allowed values of the driven attribute are ``'wire'`` and ``'reg'``.
|
|
The value specifies how the user-defined Verilog code drives the signal in
|
|
Verilog. To decide which value to use, consider how the signal should be
|
|
declared in Verilog after the user-defined code is inserted.
|
|
|
|
|