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19 lines
301 B
Verilog
19 lines
301 B
Verilog
module dff(q, d, clk, reset);
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input d;
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input clk;
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input reset;
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output q;
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reg q;
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always @(posedge clk or negedge reset) begin
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if (reset == 0) begin
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q <= 0;
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end
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else begin
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q <= d;
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end
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end // always @ (posedge clk or negedge reset)
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endmodule // inc
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