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21 lines
175 B
Verilog
21 lines
175 B
Verilog
module tb_bin2gray;
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reg [7:0] B;
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wire [7:0] G;
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initial begin
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$from_myhdl(
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B
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);
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$to_myhdl(
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G
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);
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end
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bin2gray dut(
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B,
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G
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);
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endmodule
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