mirror of
https://github.com/myhdl/myhdl.git
synced 2025-01-24 21:52:56 +08:00
3775119f83
* Move conditional so the whole job doesn't run unless it is a tag * Add dist to make and restructure release * Add message * Add message * Add message * Add message * Add message * Add message * Add message * Add message * Add message * Add README to release to appear on PyPi * Added read definition
79 lines
2.0 KiB
Makefile
79 lines
2.0 KiB
Makefile
PYTEST_OPTS ?=
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TAG ?=`grep __version__ myhdl/__init__.py | grep -oe '\([0-9.]*\)'`
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MSG ?= "Release "${TAG}
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VERSION_FILE := myhdl/__init__.py
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ANSI_RED=`tput setaf 1`
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ANSI_GREEN=`tput setaf 2`
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ANSI_CYAN=`tput setaf 6`
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ANSI_RESET=`tput sgr0`
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install:
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python setup.py install
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localinstall:
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python setup.py install --home=${HOME}
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docs:
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tox -e docs html
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livedocs:
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tox -e docs livehtml
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dist:
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rm -rf MANIFEST
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rm -rf CHANGELOG.txt
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#hg glog > CHANGELOG.txt
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python setup.py sdist
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release:
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@echo "Preparing ${TAG} - Message - ${MSG}"
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@sed -i "s|__version__ = \"[0-9.]\+\"|__version__ = \"${TAG}\"|g" ${VERSION_FILE}
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git commit --allow-empty -m ${MSG} ${VERSION_FILE}
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git tag -a ${TAG} -m ${MSG}
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git push && git push --tags
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clean:
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rm -rf *.vhd *.v *.o *.log *.hex work/ cosimulation/icarus/myhdl.vpi
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lint:
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pyflakes myhdl/
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black:
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black myhdl/
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core:
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@echo -e "\n${ANSI_CYAN}running test: $@ ${ANSI_RESET}"
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pytest ./myhdl/test/core ${PYTEST_OPTS}
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iverilog_myhdl.vpi:
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${MAKE} -C cosimulation/icarus myhdl.vpi
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iverilog_cosim: iverilog_myhdl.vpi
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${MAKE} -C cosimulation/icarus test
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iverilog_general:
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pytest ./myhdl/test/conversion/general --sim iverilog ${PYTEST_OPTS}
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iverilog_toverilog: iverilog_myhdl.vpi
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pytest ./myhdl/test/conversion/toVerilog --sim iverilog ${PYTEST_OPTS}
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iverilog_bugs:
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pytest ./myhdl/test/bugs --sim iverilog ${PYTEST_OPTS}
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iverilog: iverilog_cosim
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@echo -e "\n${ANSI_CYAN}running test: $@ ${ANSI_RESET}"
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pytest ./myhdl/test/conversion/general ./myhdl/test/conversion/toVerilog ./myhdl/test/bugs --sim iverilog ${PYTEST_OPTS}
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ghdl_general:
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pytest ./myhdl/test/conversion/general --sim ghdl ${PYTEST_OPTS}
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ghdl_tovhdl:
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pytest ./myhdl/test/conversion/toVHDL --sim ghdl ${PYTEST_OPTS}
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ghdl_bugs:
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pytest ./myhdl/test/bugs --sim ghdl ${PYTEST_OPTS}
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ghdl:
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@echo -e "\n${ANSI_CYAN}running test: $@ ${ANSI_RESET}"
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pytest ./myhdl/test/conversion/general ./myhdl/test/conversion/toVHDL ./myhdl/test/bugs --sim ghdl ${PYTEST_OPTS}
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pytest: core iverilog ghdl |