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123 lines
3.8 KiB
Plaintext
123 lines
3.8 KiB
Plaintext
MyHDL Release 0.5
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=================
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OVERVIEW
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--------
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The goal of the MyHDL project is to empower hardware designers with
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the elegance and simplicity of the Python language.
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MyHDL is a free, open-source (LGPL) package for using Python as a
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hardware description and verification language. Python is a very high
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level language, and hardware designers can use its full power to model
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and simulate their designs. Moreover, MyHDL can convert a design to
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Verilog. In combination with an external synthesis tool, it provides a
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complete path from Python to a silicon implementation.
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Modeling
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~~~~~~~~
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Python's power and clarity make MyHDL an ideal solution for high level
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modeling. Python is famous for enabling elegant solutions to complex
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modeling problems. Moreover, Python is outstanding for rapid
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application development and experimentation.
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The key idea behind MyHDL is the use of Python generators to model
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hardware concurrency. Generators are best described as resumable
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functions. In MyHDL, generators are used in a specific way so that
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they become similar to always blocks in Verilog or processes in VHDL.
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A hardware module is modeled as a function that returns any number of
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generators. This approach makes it straightforward to support features
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such as arbitrary hierarchy, named port association, arrays of
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instances, and conditional instantiation.
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Furthermore, MyHDL provides classes that implement traditional
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hardware description concepts. It provides a signal class to support
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communication between generators, a class to support bit oriented
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operations, and a class for enumeration types.
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Simulation and Verification
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~~~~~~~~~~~~~~~~~~~~~~~~~~~
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The built-in simulator runs on top of the Python interpreter. It
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supports waveform viewing by tracing signal changes in a VCD file.
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With MyHDL, the Python unit test framework can be used on hardware
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designs. Although unit testing is a popular modern software
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verification technique, it is not yet common in the hardware design
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world, making it one more area in which MyHDL innovates.
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MyHDL can also be used as hardware verification language for VHDL and
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Verilog designs, by co-simulation with traditional HDL simulators.
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Conversion to Verilog
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~~~~~~~~~~~~~~~~~~~~~
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The converter to Verilog works on an instantiated design that has been
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fully elaborated. Consequently, the original design structure can be
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arbitrarily complex.
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The converter automates certain tasks that are tedious or hard in
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Verilog directly. Notable features are the possibility to choose
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between various FSM state encodings based on a single attribute, the
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mapping of certain high-level objects to RAM and ROM descriptions, and
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the automated handling of signed arithmetic issues.
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INSTALLATION
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------------
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If you have superuser power, you can install MyHDL as follows:
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python setup.py install
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This will install the package in the appropriate site-wide Python
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package location.
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Otherwise, you can install it in a personal directory, e.g. as
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follows:
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python setup.py install --home=$HOME
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In this case, be sure to add the appropriate install dir to the
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$PYTHONPATH.
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If necessary, consult the distutils documentation in the standard
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Python library if necessary for more details; or contact me.
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You can test the proper installation as follows:
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cd myhdl/test
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python test_all.py
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To install co-simulation support:
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Go to the directory co-simulation/<platform> for your target platform
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and following the instructions in the README.txt file.
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DOCUMENTATION
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-------------
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The manual is available in various formats under the doc/
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subdirectory.
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An on-line version of the manual and extensive additional
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documentation and support information can be found on the MyHDL
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website:
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http://myhdl.jandecaluwe.com
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EXAMPLES
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--------
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See the example/ subdirectory for examples.
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AUTHOR
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------
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Jan Decaluwe <jan@jandecaluwe.com>
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