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35 lines
604 B
Python
35 lines
604 B
Python
import myhdl
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from myhdl import *
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def bin2gray(B, G, width):
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""" Gray encoder.
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B -- input intbv signal, binary encoded
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G -- output intbv signal, gray encoded
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width -- bit width
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"""
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@always_comb
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def logic():
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Bext = intbv(0)[width+1:]
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Bext[:] = B
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for i in range(width):
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G.next[i] = Bext[i+1] ^ Bext[i]
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return logic
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def main():
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width = 8
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B = Signal(intbv(0)[width:])
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G = Signal(intbv(0)[width:])
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toVerilog(bin2gray, B, G, width)
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toVHDL(bin2gray, B, G, width)
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if __name__ == '__main__':
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main()
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