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39 lines
717 B
VHDL
39 lines
717 B
VHDL
-- File: Inc.vhd
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-- Generated by MyHDL 0.6dev10
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-- Date: Sat Nov 22 22:39:37 2008
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library IEEE;
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use IEEE.std_logic_1164.all;
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use IEEE.numeric_std.all;
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use std.textio.all;
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use work.pck_myhdl_06dev10.all;
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entity Inc is
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port (
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count: inout unsigned(7 downto 0);
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enable: in std_logic;
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clock: in std_logic;
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reset: in std_logic
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);
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end entity Inc;
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architecture MyHDL of Inc is
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begin
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INC_INCLOGIC: process (clock, reset) is
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begin
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if (reset = '0') then
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count <= "00000000";
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elsif rising_edge(clock) then
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if to_boolean(enable) then
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count <= ((count + 1) mod 256);
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end if;
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end if;
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end process INC_INCLOGIC;
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end architecture MyHDL;
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