mirror of
https://github.com/myhdl/myhdl.git
synced 2025-01-24 21:52:56 +08:00
36 lines
424 B
Verilog
36 lines
424 B
Verilog
// File: ram_1.v
|
|
// Generated by MyHDL 0.6dev10
|
|
// Date: Sat Nov 22 22:39:38 2008
|
|
|
|
`timescale 1ns/10ps
|
|
|
|
module ram_1 (
|
|
dout,
|
|
din,
|
|
addr,
|
|
we,
|
|
clk
|
|
);
|
|
|
|
output [7:0] dout;
|
|
wire [7:0] dout;
|
|
input [7:0] din;
|
|
input [6:0] addr;
|
|
input we;
|
|
input clk;
|
|
|
|
|
|
reg [7:0] mem [0:128-1];
|
|
|
|
|
|
always @(posedge clk) begin: RAM_1_WRITE
|
|
if (we) begin
|
|
mem[addr] <= din;
|
|
end
|
|
end
|
|
|
|
|
|
assign dout = mem[addr];
|
|
|
|
endmodule
|