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37 lines
512 B
VHDL
37 lines
512 B
VHDL
-- File: bin2gray.vhd
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-- Generated by MyHDL 1.0dev
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-- Date: Mon May 23 16:09:27 2016
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library IEEE;
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use IEEE.std_logic_1164.all;
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use IEEE.numeric_std.all;
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use std.textio.all;
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use work.pck_myhdl_10.all;
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entity bin2gray is
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port (
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B: in unsigned(7 downto 0);
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G: out unsigned(7 downto 0)
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);
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end entity bin2gray;
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-- Gray encoder.
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--
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-- B -- binary input
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-- G -- Gray encoded output
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architecture MyHDL of bin2gray is
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begin
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G <= (shift_right(B, 1) xor B);
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end architecture MyHDL;
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