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27 lines
284 B
Verilog
27 lines
284 B
Verilog
module tb_gray_inc_reg;
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wire [7:0] graycnt;
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reg enable;
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reg clock;
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reg reset;
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initial begin
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$from_myhdl(
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enable,
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clock,
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reset
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);
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$to_myhdl(
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graycnt
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);
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end
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gray_inc_reg dut(
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graycnt,
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enable,
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clock,
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reset
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);
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endmodule
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