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78 lines
2.4 KiB
TeX
78 lines
2.4 KiB
TeX
\documentclass{manual}
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\usepackage{palatino}
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\renewcommand{\ttdefault}{cmtt}
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\renewcommand{\sfdefault}{cmss}
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\newcommand{\myhdl}{\protect \mbox{MyHDL}}
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\usepackage{graphicx}
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\title{The \myhdl\ manual}
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\input{boilerplate}
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\makeindex
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\begin{document}
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\maketitle
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\input{copyright}
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\begin{abstract}
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\noindent
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\myhdl{} is a Python package for using Python as a hardware description
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and verification language. Languages such Verilog and VHDL are
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compiled languages. Python with \myhdl{} can be viewed as a "scripting
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language" counterpart of such languages. However, Python is more
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accurately described as a very high level language (VHLL). \myhdl{} users
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have access to the amazing power and elegance of Python.
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The key idea behind \myhdl{} is to use Python generators for modeling
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hardware concurrency. A generator is a resumable function with
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internal state. In \myhdl{}, a hardware module is modeled as a function
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that returns generators. With this approach, \myhdl{} directly supports
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features such as named port association, arrays of instances, and
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conditional instantiation.
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\myhdl{} supports the classic hardware description concepts. It provides
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a signal class similar to the VHDL signal, a class for bit oriented
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operations, and support for enumeration types. The Python
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\code{yield} statement is used as a general sensitivity list to
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wait on a signal change, an edge, a delay, or on another
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generator. \myhdl{} supports waveform viewing by tracing signal changes
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in a VCD file.
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Python's rare combination of power and clarity makes it ideal for high
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level modeling. It can be expected that \myhdl{} users will often
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have the ``Pythonic experience'' of finding an elegant solution to a
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complex modeling problem. Moreover, Python is outstanding for rapid
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application development and experimentation.
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With \myhdl{}, the Python unit test framework can be used on hardware
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designs. \myhdl{} can also be used as hardware verification language for
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VHDL and Verilog designs, by co-simulation with any simulator that has
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a PLI. The distribution contains a PLI module for the
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Icarus Verilog simulator.
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The \myhdl{} software is open source software. It is licensed under the
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GNU Lesser General Public License (LGPL).
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\end{abstract}
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\tableofcontents
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\input{background.tex}
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\input{informal.tex}
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\input{modeling.tex}
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\input{unittest.tex}
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\input{cosimulation.tex}
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\input{reference.tex}
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\input{MyHDL.ind}
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\end{document}
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