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https://github.com/myhdl/myhdl.git
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124 lines
2.6 KiB
Python
124 lines
2.6 KiB
Python
from __future__ import generators
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import unittest
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from unittest import TestCase
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import random
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from random import randrange
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random.seed(2)
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from myhdl import Simulation, StopSimulation, Signal, \
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delay, intbv, negedge, posedge, now
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from dff import dff
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from dff_clkout import dff_clkout
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ACTIVE_LOW, INACTIVE_HIGH = 0, 1
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class TestDff(TestCase):
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vals = [randrange(2) for i in range(1000)]
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def clkGen(self, clk):
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while 1:
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yield delay(10)
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clk.next = not clk
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def stimulus(self, d, clk, reset):
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reset.next = ACTIVE_LOW
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yield negedge(clk)
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reset.next = INACTIVE_HIGH
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for v in self.vals:
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d.next = v
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yield negedge(clk)
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raise StopSimulation
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def check(self, q, clk, reset):
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yield posedge(reset)
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v_Z = 0
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first = 1
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for v in self.vals:
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yield posedge(clk)
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if not first:
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self.assertEqual(q, v_Z)
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first = 0
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yield delay(3)
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self.assertEqual(q, v)
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v_Z = v
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def bench(self):
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q, d, clk, reset = [Signal(intbv(0)) for i in range(4)]
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DFF_1 = dff(q, d, clk, reset)
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CLK_1 = self.clkGen(clk)
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ST_1 = self.stimulus(d, clk, reset)
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CH_1 = self.check(q, clk, reset)
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sim = Simulation(DFF_1, CLK_1, ST_1, CH_1)
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return sim
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def test1(self):
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""" dff test """
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sim = self.bench()
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sim.run(quiet=1)
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def test2(self):
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""" dff test with simulation suspends """
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sim = self.bench()
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while sim.run(duration=randrange(1,5), quiet=1):
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pass
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def bench_clkout(self):
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clkout = Signal(intbv(0))
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q = Signal(intbv(0), delay=1)
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d = Signal(intbv(0))
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clk = Signal(intbv(0))
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reset = Signal(intbv(0))
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DFF_1 = dff_clkout(clkout, q, d, clk, reset)
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CLK_1 = self.clkGen(clk)
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ST_1 = self.stimulus(d, clkout, reset)
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CH_1 = self.check(q, clkout, reset)
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sim = Simulation(DFF_1, CLK_1, ST_1, CH_1)
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return sim
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def test1_clkout(self):
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""" dff_clkout test """
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sim = self.bench_clkout()
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sim.run(quiet=1)
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def test2_clkout(self):
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""" dff_clkout test with simulation suspends """
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sim = self.bench_clkout()
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while sim.run(duration=randrange(1,5), quiet=1):
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pass
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if __name__ == '__main__':
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unittest.main()
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