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63 lines
672 B
Verilog
63 lines
672 B
Verilog
module tb_Array8Sorter;
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reg [3:0] a0;
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reg [3:0] a1;
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reg [3:0] a2;
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reg [3:0] a3;
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reg [3:0] a4;
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reg [3:0] a5;
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reg [3:0] a6;
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reg [3:0] a7;
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wire [3:0] z0;
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wire [3:0] z1;
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wire [3:0] z2;
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wire [3:0] z3;
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wire [3:0] z4;
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wire [3:0] z5;
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wire [3:0] z6;
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wire [3:0] z7;
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initial begin
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$from_myhdl(
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a0,
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a1,
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a2,
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a3,
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a4,
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a5,
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a6,
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a7
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);
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$to_myhdl(
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z0,
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z1,
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z2,
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z3,
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z4,
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z5,
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z6,
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z7
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);
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end
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Array8Sorter dut(
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a0,
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a1,
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a2,
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a3,
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a4,
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a5,
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a6,
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a7,
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z0,
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z1,
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z2,
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z3,
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z4,
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z5,
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z6,
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z7
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);
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endmodule
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