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16 lines
425 B
Python
16 lines
425 B
Python
from myhdl import Signal, ResetSignal, modbv
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from gray_inc_reg import gray_inc_reg
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def convert_gray_inc_reg(hdl, width=8):
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graycnt = Signal(modbv(0)[width:])
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enable = Signal(bool())
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clock = Signal(bool())
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reset = ResetSignal(0, active=0, isasync=True)
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inst = gray_inc_reg(graycnt, enable, clock, reset, width)
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inst.convert(hdl)
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convert_gray_inc_reg(hdl='Verilog')
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convert_gray_inc_reg(hdl='VHDL')
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