oh/scripts/build.sh

#!/bin/bash

############################################################################
# Icarus Verilog build script for OH! 
#
# Requires $OH_HOME variable to be set
#
# Example: ./scripts/build.sh elink/hdl/dut_elink.v
#
############################################################################

DUT=$1

##############################
#Create directory of all links
##############################
$OH_HOME/scripts/link.sh

##############################
#Build
###############################
iverilog -g2005\
 -DTARGET_SIM=1\
 -DCFG_ASIC=0\
 -DCFG_PLATFORM=\"ZYNQ\"\
 $DUT\
 $OH_HOME/symlinks/dv/dv_top.v\
 -y .\
 -y $OH_HOME/symlinks/hdl\
 -y $OH_HOME/symlinks/dv\
 -I $OH_HOME/symlinks/hdl\
 -o dut.bin\
Putting simplified scripts in $OH_HOME 2016-03-08 15:49:15 -05:00			`#!/bin/bash`

			`############################################################################`
			`# Icarus Verilog build script for OH!`
Reorg cleanup 2016-03-22 08:27:59 -04:00			`#`
Putting simplified scripts in $OH_HOME 2016-03-08 15:49:15 -05:00			`# Requires $OH_HOME variable to be set`
Reorg cleanup 2016-03-22 08:27:59 -04:00			`#`
			`# Example: ./scripts/build.sh elink/hdl/dut_elink.v`
			`#`
Putting simplified scripts in $OH_HOME 2016-03-08 15:49:15 -05:00			`############################################################################`

			`DUT=$1`

			`##############################`
			`#Create directory of all links`
			`##############################`
Reorg cleanup 2016-03-22 08:27:59 -04:00			`$OH_HOME/scripts/link.sh`

Putting simplified scripts in $OH_HOME 2016-03-08 15:49:15 -05:00			`##############################`
			`#Build`
			`###############################`
			`iverilog -g2005\`
			`-DTARGET_SIM=1\`
Making CFG_ASIC a primary variable -Need to separate between open FPGA design and closed ASIC design. -NDAs means it's imposssible for us to disclose even the interfaces of the cells inside without taking the risk of violating the terms of the NDA. -For this reason, we come up with generic and clean asic library interfaces that need to be implemented in each library/technology 2016-06-19 17:05:50 -04:00			`-DCFG_ASIC=0\`
Fixed elink platform compile errors -Ultrascale changes broke the zynq design -Adding CFG_PLATFORM variable to control compilation target 2017-11-22 11:32:20 -05:00			`-DCFG_PLATFORM=\"ZYNQ\"\`
Putting simplified scripts in $OH_HOME 2016-03-08 15:49:15 -05:00			`$DUT\`
			`$OH_HOME/symlinks/dv/dv_top.v\`
			`-y .\`
			`-y $OH_HOME/symlinks/hdl\`
			`-y $OH_HOME/symlinks/dv\`
			`-I $OH_HOME/symlinks/hdl\`
			`-o dut.bin\`