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# OH! : Open Hardware for FPGA and ASIC designers
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![alt tag ](common/docs/lego.jpg )
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## CONTENT
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| Module | Status | Description |
|----------------------------|---------|------------------------------------------|
| [accelerator ](accelerator ) | FPGA | Accelerator tutorial |
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| [chip ](chip ) | SILICON | Chip design reference flow |
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| [common ](common ) | SILICON*| Library of generally useful components |
| [emesh ](emesh ) | SILICON | Emesh interface utility circuits |
| [elink ](elink ) | SILICON | Point to point LVDS link |
| [emailbox ](emailbox ) | FPGA | Mailbox with interrupt output |
| [emmu ](emmu ) | FPGA | Memory transaction translation unit |
| [irqc ](irqc ) | SILICON | Epiphany nested interrupt controller |
| [xilibs ](xilibs ) | FPGA | Simulation modules for Xilinx primitives |
**NOTES:**
* "SILICON": Silicon validated
* "FPGA": FPGA validated
* "SIM": Simulation only
* Common folder includes modules with mixed status. Some are silicon validated, others have only been simulated.
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## LICENSE
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The OH! repository source code is licensed under the MIT license unless otherwise specified. See [LICENSE ](LICENSE ) for MIT copyright terms. Design specific licenses can be found in the folder root (eg: aes/LICENSE)
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## CONTRIBUTING
Instructions for contributing can be found [HERE ](CONTRIBUTING.md ).
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## RECOMMEND TOOLS
* [Verilator Simulator ](http://www.veripool.org/wiki/verilator )
* [Emacs Verilog Mode ](http://www.veripool.org/wiki/verilog-mode )
* [Icarus Simulator ](http://iverilog.icarus.com )
* [GTKWave ](http://gtkwave.sourceforge.net )
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* [Wavedrom ](http://wavedrom.com/editor.html )
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## RECOMMENDED READING
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* [Glossary ](chip/docs/glossary.md )
* [Chip constants ](chip/docs/constants.md )
* [Verilog Reference ](verilog/verilog_reference.md )
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[picture-license ](https://commons.wikimedia.org/wiki/File:Lego_Color_Bricks.jpg )
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