oh/.gitignore

######################
# Compiled binaries
*.elf
*.o
*.e
*.d
######################
# Emacs/vim/gedit backup files
*~
.*.swp
.*.swo
*#
*.bak

#######################
# Simulation files
*.vvp
*.vcd
*.out
*.trace

#######################
# XILINX crap
*.log
*.jou
*.runs
*.sim
*.rpt
*.str
*.xml
*.hw
*.cache
xgui/
*.zip
*_stub.vhdl
*.upgrade_log
*_stub.v
*_changelog.txt
Cleanup 2015-04-21 21:43:16 -04:00			`######################`
			`# Compiled binaries`
			`*.elf`
			`*.o`
			`*.e`
			`*.d`
			`######################`
			`# Emacs/vim/gedit backup files`
			`*~`
			`.*.swp`
			`.*.swo`
			`*#`
			`*.bak`

			`#######################`
Stimulus end of test issue - Still not 100% on this...but test passes - Teset was hanging even though stim_done went high. Ticks not advancing, pointing towards comb loop, but what is different at end of test? - Now to test read/writes of registers from axi and set the idelay registers 2015-11-03 19:56:27 -05:00			`# Simulation files`
			`*.vvp`
			`*.vcd`
			`*.out`
			`*.trace`
Simulation file cleanup 2015-11-03 19:53:43 -05:00
			`#######################`
Added filters for all the Xilinx junk - git should have only .tcl files really... 2015-11-04 17:55:01 -05:00			`# XILINX crap`
Cleanup 2015-04-21 21:43:16 -04:00			`*.log`
			`*.jou`
Simulation file cleanup 2015-11-03 19:53:43 -05:00			`*.runs`
			`*.sim`
			`*.rpt`
Added filters for all the Xilinx junk - git should have only .tcl files really... 2015-11-04 17:55:01 -05:00			`*.str`
			`*.xml`
			`*.hw`
			`*.cache`
			`xgui/`
			`*.zip`
Filtering more Xilinx junk files 2015-11-04 19:18:11 -05:00			`*_stub.vhdl`
			`*.upgrade_log`
			`*_stub.v`
			`*_changelog.txt`
Added filters for all the Xilinx junk - git should have only .tcl files really... 2015-11-04 17:55:01 -05:00