oh/stdlib/testbench/run.sh

#!/bin/bash


# LFSR
iverilog -DOH_CTRL="8'h12" -DOH_N=5  sim.v tb_oh_lfsr.v -y ../rtl/ -y . ; ./a.out
iverilog -DOH_CTRL="8'h9"  -DOH_N=4  sim.v tb_oh_lfsr.v -y ../rtl/ -y . ; ./a.out
Adding missing files 2015-11-03 14:16:50 -05:00			`#!/bin/bash`
Adding clk90 output to clkdiv -Added testbench -Needs more review! 2016-02-23 17:49:08 -05:00
Adding "SEED" as basic parameter -making randomness clocks a first class citizen -Verilog doesn't have a seed, need to drive it from the shell -a must for async clocks, useful for many things -does not preclude randomization externally as well 2016-02-24 14:21:04 -05:00
Finishing minimal icarus "standardized" testbench - Driving all values from the command line - Standardizing around "OH_" to avoid name conflicts - Driving seed as a parameter value 2022-06-28 23:18:00 -04:00			`# LFSR`
			`iverilog -DOH_CTRL="8'h12" -DOH_N=5 sim.v tb_oh_lfsr.v -y ../rtl/ -y . ; ./a.out`
			`iverilog -DOH_CTRL="8'h9" -DOH_N=4 sim.v tb_oh_lfsr.v -y ../rtl/ -y . ; ./a.out`