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36 lines
657 B
Coq
36 lines
657 B
Coq
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//Variable pipeline depth syncrhonizer
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module dsync (/*AUTOARG*/
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// Outputs
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dout,
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// Inputs
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clk, din
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);
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parameter PS = 2; //number of sync pipeline stages
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parameter DW = 1; //number of bits to synchronize
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input clk;
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input [DW-1:0] din;
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output [DW-1:0] dout;
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reg [PS-1:0] sync_pipe[DW-1:0];
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genvar i;
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integer j;
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generate
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for(i=0;i<DW;i=i+1)
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begin
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always @ (posedge clk)
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begin
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sync_pipe[i][0] = din;
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for(j=1;j<PS;j=j+1)
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sync_pipe[i][j] = sync_pipe[i][j-1];
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end
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assign dout[i] = sync_pipe[i][PS-1];
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end
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endgenerate
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endmodule // dsync
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