oh/elink/dv/build.sh

#!/bin/bash
#
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dut="elink"
top="../../common/dv/dv_top.v"
iverilog -g2005 -DTARGET_SIM=1 -DTARGET_XILINX=1  ../../memory/fpga/fifo_generator_v12_0/simulation/fifo_generator_vlog_beh.v  ../../memory/fpga/sim/fifo_async_104x32.v  $top dut_${dut}.v -f ../../common/dv/libs.cmd -o ${dut}.vvp

#PUT TARGET_SIM 

#-pfileline=1
#-Wall
Stupid typos.. 2015-11-09 16:18:20 -05:00			`#!/bin/bash`
			`#`
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			`dut="elink"`
			`top="../../common/dv/dv_top.v"`
Changing build script to work with xilinx model 2015-11-12 00:56:02 -05:00			`iverilog -g2005 -DTARGET_SIM=1 -DTARGET_XILINX=1 ../../memory/fpga/fifo_generator_v12_0/simulation/fifo_generator_vlog_beh.v ../../memory/fpga/sim/fifo_async_104x32.v $top dut_${dut}.v -f ../../common/dv/libs.cmd -o ${dut}.vvp`
Stupid typos.. 2015-11-09 16:18:20 -05:00
Cleanup 2015-11-09 20:39:48 -05:00			`#PUT TARGET_SIM`
Stupid typos.. 2015-11-09 16:18:20 -05:00
			`#-pfileline=1`
			`#-Wall`