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29 lines
617 B
Tcl
29 lines
617 B
Tcl
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# NOTE: See UG1118 for more information
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#########################################
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# VARIABLES
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#########################################
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set design parallella_base
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set projdir ./
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set root "../../.."
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set partname "xc7z020clg400-1"
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set hdl_files [list \
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$root/common/hdl \
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$root/memory/hdl \
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$root/emesh/hdl \
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$root/emmu/hdl \
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$root/emailbox/hdl \
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$root/edma/hdl \
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$root/elink/hdl \
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$root/parallella/hdl \
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$root/parallella/hdl/parallella_base.v \
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]
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set ip_files [list \
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$root/memory/fpga/fifo_async_104x32.xci \
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]
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set constraints_files []
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