oh/parallella/package/xilinx/parallella_ps.tcl

################################################################
# This is a generated script based on design: design_1
#
# Though there are limitations about the generated script,
# the main purpose of this utility is to make learning
# IP Integrator Tcl commands easier.
################################################################

################################################################
# Check if script is running in correct Vivado version.
################################################################
set scripts_vivado_version 2014.2
set current_vivado_version [version -short]

if { [string first $scripts_vivado_version $current_vivado_version] == -1 } {
   puts ""
   puts "ERROR: This script was generated using Vivado <$scripts_vivado_version> and is being run in <$current_vivado_version> of Vivado. Please run the script in Vivado <$scripts_vivado_version> then open the design in Vivado <$current_vivado_version>. Upgrade the design by running \"Tools => Report => Report IP Status...\", then run write_bd_tcl to create an updated script."

   return 1
}

################################################################
# START
################################################################

# To test this script, run the following commands from Vivado Tcl console:
# source design_1_script.tcl

# If you do not already have a project created,
# you can create a project using the following command:
#    create_project project_1 myproj -part xc7z020clg400-1


# CHANGE DESIGN NAME HERE
#set design_name design_1
set design_name system

# If you do not already have an existing IP Integrator design open,
# you can create a design using the following command:
#    create_bd_design $design_name

# CHECKING IF PROJECT EXISTS
if { [get_projects -quiet] eq "" } {
   puts "ERROR: Please open or create a project!"
   return 1
}


# Creating design if needed
set errMsg ""
set nRet 0

set cur_design [current_bd_design -quiet]
set list_cells [get_bd_cells -quiet]

if { ${design_name} ne "" && ${cur_design} eq ${design_name} } {

   # Checks if design is empty or not
   if { $list_cells ne "" } {
      set errMsg "ERROR: Design <$design_name> already exists in your project, please set the variable <design_name> to another value."
      set nRet 1
   } else {
      puts "INFO: Constructing design in IPI design <$design_name>..."
   }
} elseif { ${cur_design} ne "" && ${cur_design} ne ${design_name} } {

   if { $list_cells eq "" } {
      puts "INFO: You have an empty design <${cur_design}>. Will go ahead and create design..."
   } else {
      set errMsg "ERROR: Design <${cur_design}> is not empty! Please do not source this script on non-empty designs."
      set nRet 1
   }
} else {

   if { [get_files -quiet ${design_name}.bd] eq "" } {
      puts "INFO: Currently there is no design <$design_name> in project, so creating one..."

      create_bd_design $design_name

      puts "INFO: Making design <$design_name> as current_bd_design."
      current_bd_design $design_name

   } else {
      set errMsg "ERROR: Design <$design_name> already exists in your project, please set the variable <design_name> to another value."
      set nRet 3
   }

}

puts "INFO: Currently the variable <design_name> is equal to \"$design_name\"."

if { $nRet != 0 } {
   puts $errMsg
   return $nRet
}

##################################################################
# DESIGN PROCs
##################################################################



# Procedure to create entire design; Provide argument to make
# procedure reusable. If parentCell is "", will use root.
proc create_root_design { parentCell } {

  if { $parentCell eq "" } {
     set parentCell [get_bd_cells /]
  }

  # Get object for parentCell
  set parentObj [get_bd_cells $parentCell]
  if { $parentObj == "" } {
     puts "ERROR: Unable to find parent cell <$parentCell>!"
     return
  }

  # Make sure parentObj is hier blk
  set parentType [get_property TYPE $parentObj]
  if { $parentType ne "hier" } {
     puts "ERROR: Parent <$parentObj> has TYPE = <$parentType>. Expected to be <hier>."
     return
  }

  # Save current instance; Restore later
  set oldCurInst [current_bd_instance .]

  # Set parent object as current
  current_bd_instance $parentObj


  # Create interface ports

  # Create ports

  # Create instance: sys_ps7, and set properties
  global sys_ps7
# Linus : already created 
#  set sys_ps7 [ create_bd_cell -type ip -vlnv xilinx.com:ip:processing_system7:5.4 sys_ps7 ]
  set_property -dict [ list CONFIG.PCW_ACT_APU_PERIPHERAL_FREQMHZ {666.666687} CONFIG.PCW_ACT_CAN_PERIPHERAL_FREQMHZ {10.000000} CONFIG.PCW_ACT_DCI_PERIPHERAL_FREQMHZ {10.062893} CONFIG.PCW_ACT_ENET0_PERIPHERAL_FREQMHZ {125.000000} CONFIG.PCW_ACT_ENET1_PERIPHERAL_FREQMHZ {10.000000} CONFIG.PCW_ACT_FPGA0_PERIPHERAL_FREQMHZ {100.000000} CONFIG.PCW_ACT_FPGA1_PERIPHERAL_FREQMHZ {200.000000} CONFIG.PCW_ACT_FPGA2_PERIPHERAL_FREQMHZ {200.000000} CONFIG.PCW_ACT_FPGA3_PERIPHERAL_FREQMHZ {40.000000} CONFIG.PCW_ACT_I2C_PERIPHERAL_FREQMHZ {50} CONFIG.PCW_ACT_PCAP_PERIPHERAL_FREQMHZ {200.000000} CONFIG.PCW_ACT_QSPI_PERIPHERAL_FREQMHZ {200.000000} CONFIG.PCW_ACT_SDIO_PERIPHERAL_FREQMHZ {50.000000} CONFIG.PCW_ACT_SMC_PERIPHERAL_FREQMHZ {10.000000} CONFIG.PCW_ACT_SPI_PERIPHERAL_FREQMHZ {10.000000} CONFIG.PCW_ACT_TPIU_PERIPHERAL_FREQMHZ {200.000000} CONFIG.PCW_ACT_TTC0_CLK0_PERIPHERAL_FREQMHZ {111.111115} CONFIG.PCW_ACT_TTC0_CLK1_PERIPHERAL_FREQMHZ {111.111115} CONFIG.PCW_ACT_TTC0_CLK2_PERIPHERAL_FREQMHZ {111.111115} CONFIG.PCW_ACT_TTC1_CLK0_PERIPHERAL_FREQMHZ {111.111115} CONFIG.PCW_ACT_TTC1_CLK1_PERIPHERAL_FREQMHZ {111.111115} CONFIG.PCW_ACT_TTC1_CLK2_PERIPHERAL_FREQMHZ {111.111115} CONFIG.PCW_ACT_TTC_PERIPHERAL_FREQMHZ {50} CONFIG.PCW_ACT_UART_PERIPHERAL_FREQMHZ {100.000000} CONFIG.PCW_ACT_USB0_PERIPHERAL_FREQMHZ {60} CONFIG.PCW_ACT_USB1_PERIPHERAL_FREQMHZ {60} CONFIG.PCW_ACT_WDT_PERIPHERAL_FREQMHZ {111.111115} CONFIG.PCW_APU_CLK_RATIO_ENABLE {6:2:1} CONFIG.PCW_APU_PERIPHERAL_FREQMHZ {666.666666} CONFIG.PCW_ARMPLL_CTRL_FBDIV {40} CONFIG.PCW_CAN0_BASEADDR {0xE0008000} CONFIG.PCW_CAN0_CAN0_IO {<Select>} CONFIG.PCW_CAN0_GRP_CLK_ENABLE {0} CONFIG.PCW_CAN0_GRP_CLK_IO {<Select>} CONFIG.PCW_CAN0_HIGHADDR {0xE0008FFF} CONFIG.PCW_CAN0_PERIPHERAL_CLKSRC {External} CONFIG.PCW_CAN0_PERIPHERAL_ENABLE {0} CONFIG.PCW_CAN0_PERIPHERAL_FREQMHZ {-1} CONFIG.PCW_CAN1_BASEADDR {0xE0009000} CONFIG.PCW_CAN1_CAN1_IO {<Select>} CONFIG.PCW_CAN1_GRP_CLK_ENABLE {0} CONFIG.PCW_CAN1_GRP_CLK_IO {<Select>} CONFIG.PCW_CAN1_HIGHADDR {0xE0009FFF} CONFIG.PCW_CAN1_PERIPHERAL_CLKSRC {External} CONFIG.PCW_CAN1_PERIPHERAL_ENABLE {0} CONFIG.PCW_CAN1_PERIPHERAL_FREQMHZ {-1} CONFIG.PCW_CAN_PERIPHERAL_CLKSRC {IO PLL} CONFIG.PCW_CAN_PERIPHERAL_DIVISOR0 {1} CONFIG.PCW_CAN_PERIPHERAL_DIVISOR1 {1} CONFIG.PCW_CAN_PERIPHERAL_FREQMHZ {100} CONFIG.PCW_CAN_PERIPHERAL_VALID {0} CONFIG.PCW_CLK0_FREQ {100000000} CONFIG.PCW_CLK1_FREQ {200000000} CONFIG.PCW_CLK2_FREQ {200000000} CONFIG.PCW_CLK3_FREQ {40000000} CONFIG.PCW_CORE0_FIQ_INTR {0} CONFIG.PCW_CORE1_FIQ_INTR {0} CONFIG.PCW_CPU_CPU_6X4X_MAX_RANGE {667} CONFIG.PCW_CPU_CPU_PLL_FREQMHZ {1333.333} CONFIG.PCW_CPU_PERIPHERAL_CLKSRC {ARM PLL} CONFIG.PCW_CPU_PERIPHERAL_DIVISOR0 {2} CONFIG.PCW_CRYSTAL_PERIPHERAL_FREQMHZ {33.333333} CONFIG.PCW_DCI_PERIPHERAL_CLKSRC {DDR PLL} CONFIG.PCW_DCI_PERIPHERAL_DIVISOR0 {53} CONFIG.PCW_DCI_PERIPHERAL_DIVISOR1 {3} CONFIG.PCW_DCI_PERIPHERAL_FREQMHZ {10.159} CONFIG.PCW_DDRPLL_CTRL_FBDIV {48} CONFIG.PCW_DDR_DDR_PLL_FREQMHZ {1600.000} CONFIG.PCW_DDR_HPRLPR_QUEUE_PARTITION {HPR(0)/LPR(32)} CONFIG.PCW_DDR_HPR_TO_CRITICAL_PRIORITY_LEVEL {15} CONFIG.PCW_DDR_LPR_TO_CRITICAL_PRIORITY_LEVEL {2} CONFIG.PCW_DDR_PERIPHERAL_CLKSRC {DDR PLL} CONFIG.PCW_DDR_PERIPHERAL_DIVISOR0 {4} CONFIG.PCW_DDR_PORT0_HPR_ENABLE {0} CONFIG.PCW_DDR_PORT1_HPR_ENABLE {0} CONFIG.PCW_DDR_PORT2_HPR_ENABLE {0} CONFIG.PCW_DDR_PORT3_HPR_ENABLE {0} CONFIG.PCW_DDR_PRIORITY_READPORT_0 {<Select>} CONFIG.PCW_DDR_PRIORITY_READPORT_1 {<Select>} CONFIG.PCW_DDR_PRIORITY_READPORT_2 {<Select>} CONFIG.PCW_DDR_PRIORITY_READPORT_3 {<Select>} CONFIG.PCW_DDR_PRIORITY_WRITEPORT_0 {<Select>} CONFIG.PCW_DDR_PRIORITY_WRITEPORT_1 {<Select>} CONFIG.PCW_DDR_PRIORITY_WRITEPORT_2 {<Select>} CONFIG.PCW_DDR_PRIORITY_WRITEPORT_3 {<Select>} CONFIG.PCW_DDR_RAM_BASEADDR {0x00100000} CONFIG.PCW_DDR_RAM_HIGHADDR {0x3FFFFFFF} CONFIG.PCW_DDR_WRITE_TO_CRITICAL_PRIORITY_LEVEL {2} CONFIG.PCW_DM_WIDTH {4} CONFIG.PCW_DQS_WIDTH {4} CONFIG.PCW_DQ_WIDTH {32} CONFIG.PCW_ENET0_BASEADDR {0xE000B000} CONFIG.PCW_ENET0_ENET0_IO {MIO 16 .. 27} CONFIG.PCW_ENET0_GRP_MDIO_ENABLE {1} CONFIG.PCW_ENET0_G

  # Create port connections

  # Create address segments
  

  # Restore current instance
  current_bd_instance $oldCurInst

  save_bd_design
}
# End of create_root_design()


##################################################################
# MAIN FLOW
##################################################################

create_root_design ""