oh/elink/dv/elink.cmd

dv_elink.v
../../constants/hdl/xilinx_constants.v
../../elink/hdl/elink_regmap.v
-y .
-y ../../elink/hdl
-y ../../stubs/hdl
-y ../../common/hdl
-y ../../axi/hdl
-y ../../memory/hdl
-y ../../embox/hdl
-y ../../emmu/hdl
-y ../../ecfg/hdl
-y ../../erx/hdl
-y ../../etx/hdl
-y ../../eclock/hdl
Fixing typo 2015-03-23 15:46:56 -04:00			`dv_elink.v`
Vivado run through -missed connections -mismatched bus widths -missing IP blocks -cleanup -proper DV starts tomorrow 2015-04-08 23:40:16 -04:00			`../../constants/hdl/xilinx_constants.v`
Major cleanup, refactoring, and feature completion -adding clock bypass mode for esystx[12] -removing monitor feature on erx -remove loopback support from doc -add clock bypass mode for esysclk -shortening register names (descriptive enough) -added debug signal information -moving registers to elink -making elink version programmable (to support plug in boards) -reorganized debug signals and added stickys -added timeout for axi slave -removed embox status bit (redudant, don't poll status) -renamed EMBOX0-->EMBOXLO -moved datain interface straight to ecfg (cleanup) -changed etx arbiter priority to increase stability -created the esaxi_mux block -fixed some missing ports issues in stubs Now comes the fun part...verification... Andreas 2015-04-11 00:04:18 -04:00			`../../elink/hdl/elink_regmap.v`
Fixing typo 2015-03-23 15:46:56 -04:00			`-y .`
			`-y ../../elink/hdl`
Massive checkin... -this may break already broken projects -creates a Verilog top level (instead of using Vivado block level design) -integrates mmy and mailbox (not completely integrated) -compiles... -pours in all of the code from the archive (some new logic created) 2015-03-24 20:44:03 -04:00			`-y ../../stubs/hdl`
Adding fofo environment for elink to check for broken signals. Too many stub modules to be practical..next need sim models 2014-12-14 22:17:23 -05:00			`-y ../../common/hdl`
			`-y ../../axi/hdl`
			`-y ../../memory/hdl`
			`-y ../../embox/hdl`
			`-y ../../emmu/hdl`
Massive checkin... -this may break already broken projects -creates a Verilog top level (instead of using Vivado block level design) -integrates mmy and mailbox (not completely integrated) -compiles... -pours in all of the code from the archive (some new logic created) 2015-03-24 20:44:03 -04:00			`-y ../../ecfg/hdl`
Adding fofo environment for elink to check for broken signals. Too many stub modules to be practical..next need sim models 2014-12-14 22:17:23 -05:00			`-y ../../erx/hdl`
			`-y ../../etx/hdl`
Refactoring and fixing bugs... -back and forth with emmu, memory is now inside (for good) -renamed clocks in etx to clarify -updated logic in protocol and disty -updated clock module ...one more review pass and we are ready for testing... 2015-03-25 19:25:12 -04:00			`-y ../../eclock/hdl`
Verilator inspired bug fixes -address width in elink -bus widths in ecfg -command file more generic 2014-12-15 15:25:09 -05:00