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50 lines
1.5 KiB
Systemverilog
50 lines
1.5 KiB
Systemverilog
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//#############################################################################
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//# Function: 2 Input Nand Gate #
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//# Copyright: OH Project Authors. ALl rights Reserved. #
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//# License: MIT (see LICENSE file in OH repository) #
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//#############################################################################
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module oh_nand2
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#(parameter SIM = "rtl",
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parameter NMODEL = "nmos",
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parameter PMODEL = "pmos",
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parameter N = 4,
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parameter integer W[N-1:0] = '{0, 0, 0, 0}, //nanometers
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parameter integer L[N-1:0] = '{0, 0, 0, 0}, //nanometers
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parameter integer M[N-1:0] = '{1, 1, 1, 1},
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parameter integer NF[N-1:0] = '{1, 1, 1, 1}
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)
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(
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input vdd,
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input vss,
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input a,
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input b,
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output z
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);
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generate
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if(SIM=="rtl")
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begin
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assign z = ~(a & b);
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end
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else
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begin
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wire inet;
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oh_nmos #(.MODEL(NMODEL),.W(W[0]),.L(L[0]),.M(M[0]), .NF(NF[0]))
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m0 (.d(inet), .g(a), .s(vss), .bulk(vss));
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oh_nmos #(.MODEL(NMODEL),.W(W[1]),.L(L[1]),.M(M[1]), .NF(NF[1]))
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m1 (.d(z), .g(b), .s(inet), .bulk(vss));
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oh_pmos #(.MODEL(PMODEL),.W(W[2]),.L(L[2]),.M(M[2]), .NF(NF[2]))
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m2 (.d(z), .g(a), .s(vdd), .bulk(vdd));
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oh_pmos #(.MODEL(PMODEL),.W(W[3]),.L(L[3]),.M(M[3]), .NF(NF[3]))
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m3 (.d(z), .g(b), .s(vdd), .bulk(vdd));
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end
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endgenerate
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endmodule
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