2016-05-31 13:19:26 -04:00
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| Project Management | Answer |
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| Was git used for source control? | |
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| Were all sources under version control? | |
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| Were tapeout reports saved in src tree? | |
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| Was tapeout db archived and tagged? | |
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| Specification | Answer |
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|--------------------------------------------|--------------------------------|
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| Is there a written specification? | |
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2016-05-31 13:24:40 -04:00
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| Is the datasheet complete and accurate? | |
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| Is there a user guide? | |
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2016-05-31 13:19:26 -04:00
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| What is the chip max power target? | |
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| What is the chip standby power target? | |
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| What is the chip yield target? | |
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| What is the chip cost target? | |
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| What is the max die size? | |
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2016-05-31 13:24:40 -04:00
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| What is the maximum die size? | |
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2016-05-31 13:19:26 -04:00
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| How many signal IOs? | |
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| What is the highest frequency IO? | |
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| Design | Answer |
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|--------------------------------------------|--------------------------------|
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| In Verilog 2005 used? | |
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2016-05-31 13:31:34 -04:00
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| Are all features implemented? | |
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| Are all issues closed? | |
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| Has design been through peer review? | |
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2016-05-31 13:19:26 -04:00
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| Has a linter been run? | |
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| Is there zero use of 'casex'? | |
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| Were Latches used? (If so list) | |
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| Were negedge flops used? (If so list) | |
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| Do all blocks have a license header? | |
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| Are all interface signals described? | |
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| Was naming methodology followed? | |
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| Lower case for all signals? | |
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| Upper case for parameters/defines? | |
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| Max 80 character line lengths? | |
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| Case or and/or style muxes used? | |
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| Non-blocking used for all states? | |
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| Was instantiation by name used? | |
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| Does each file contain one module | |
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| Is HDL reuse maximized? | |
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| Has design been through peer review? | |
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| Are all signals connected? | |
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| Any floating inputs in design? | |
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| All power-gated signals isolated? | |
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| All voltage domain crossings levelshifted? | |
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2016-05-31 13:31:34 -04:00
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| Is Verilog 2005 used? | |
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2016-05-31 13:19:26 -04:00
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| Verification | Answer |
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|--------------------------------------------|--------------------------------|
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| 100% HDL Code Coverage? | |
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| 100% Unit Test Covergage? | |
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| Random verifiation used? | |
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| >24hrs of random vectors? | |
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| Randomized clock frequencies? | |
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| Were all open issues closed? | |
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2016-06-20 21:21:07 -04:00
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2016-05-31 13:31:34 -04:00
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| Were all features tested? | |
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2016-05-31 13:19:26 -04:00
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| Simulator support for all features? | |
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| Was design emulated in an FPGA? | |
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| Was design validated with application SW? | |
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| Was formal equivalence run between HDL/GL? | |
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2016-05-31 13:24:40 -04:00
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| Is the firmware written? | |
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| Is there a demo? | |
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2016-06-20 21:21:07 -04:00
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2016-05-31 13:19:26 -04:00
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| Timing | Answer |
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|--------------------------------------------|--------------------------------|
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| All paths constrained? | |
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| All clocks defined? | |
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| Max transition defined? | |
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| Hold margin added? | |
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| False paths reviewed/proven? | |
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| Setup time met? | |
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| Hold time met? | |
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| All paths constrained? | |
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| Was clock path pessimism removed? | |
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| Was vmin/vmax verified? | |
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| Was Tmin/Tmax verified? | |
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| Was FF/SS/TT verified? | |
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| On chip variability accounted for? | |
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| What other corners/modes were verified? | |
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| Clock | Answer |
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|--------------------------------------------|--------------------------------|
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| Percentage regs clock gated? | |
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2016-05-31 13:31:34 -04:00
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| Integrated clock gating cells used? | |
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| Setup/hold verified on clock gating cells? | |
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2016-05-31 13:19:26 -04:00
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| Clock tree insertion delay? | |
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| Clock tree local skew? | |
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| Clock tree global skew? | |
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| Clock tree manually reviewed? | |
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| Double pitch/shield on main branch? | |
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| List of all clock domain crossings? | |
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| Use of oh_fifo_cdc on all CDCs? | |
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| Were custom CDCs used? (if so list) | |
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| Reset | Answer |
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|--------------------------------------------|--------------------------------|
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| Is reset active low used? | |
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| Is reset of type async entry, sync exit? | |
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| Are all reset pins synchronized? | |
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| Was oh_rsync used for every clk domain | |
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| Is use of reset minimized? | |
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| Total fanout of reset signal? | |
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| Power | Answer |
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|--------------------------------------------|--------------------------------|
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| Is a power mesh used? | |
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| What is the simulated IR drop? | |
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| Was dynamic IR drop analysis run? | |
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| Were package parasitics simulated? | |
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| Does chip follow IP/foundry guidelines? | |
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| Standby power goal validated in simulation?| |
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| Peak power goal validated in simulation? | |
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| IO | Answer |
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|--------------------------------------------|--------------------------------|
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| Were ESD guidelines followed? | |
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| Were IO layout guidelines followed? | |
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| Was the IO reviewed by package team? | |
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| Are there sufficient power/gnd bumps | |
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| Can assembly team meet pitch requirements? | |
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| What packaging style will be used? | |
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| Wirebond pad/pitch (if any)? | |
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| Flip-chip pad/pitch(if any)? | |
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| IP | |
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|--------------------------------------------|--------------------------------|
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| Is all external IP silicon proven? | |
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| Are IP characterization reports available? | |
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| Is the latest version IP being used? | |
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| Was the IP verilog model used for DV? | |
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| Wast the IP simulated in full-chip env? | |
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| Did you read all the documents? | |
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| Are there any open document questions? | |
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| Are all IP design checklists met? | |
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| Synthesis | Answer |
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|--------------------------------------------|--------------------------------|
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| Was the correct/latest version of HDL used?| |
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| Are all EDA warnings/errors acceptable? | |
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| The number of warnings has bee minimized? | |
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| Layout | Answer |
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|--------------------------------------------|--------------------------------|
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2016-05-31 13:24:40 -04:00
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| Synthesis/PNR | Answer |
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|--------------------------------------------|--------------------------------|
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| Is the flow completely automated? | |
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| Was the correct/latest version of HDL used?| |
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| Are all EDA warnings/errors acceptable? | |
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| The number of warnings has bee minimized? | |
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2016-05-31 13:19:26 -04:00
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| Was the correct/latest gate level used? | |
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| Are all EDA warnings/errors understood? | |
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| Are ECO/spare cells used? | |
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| Were boundary cells included? | |
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| Were decoupling caps used? | |
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| How many placed instances? | |
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| What is the logic utilization? | |
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| Is block DRC clean? | |
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| List any DRC violations? | |
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| Is block LVS clean? | |
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| List any LVS violations? | |
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| Were the final foundry masks reviewed? | |
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| Were the minimal number of metals used? | |
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| Is the chip ring included | |
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| Is the chip logo included | |
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| Have gds layer map been manually reviewed? | |
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| Has tapeout GDS been manually reviewed? | |
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2016-05-31 13:31:34 -04:00
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| XOR check between foundry/design GDSIIs | |
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2016-05-31 13:19:26 -04:00
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| DFM | Answer |
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|--------------------------------------------|--------------------------------|
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| Were all foundry DFM guidlines followed? | |
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| Is column repair included in SRAM? | |
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| What is the percentage of double vias? | |
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| Is yield optimizing wire spreading used? | |
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| Does design include fault tolerance? | |
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2016-05-31 13:31:34 -04:00
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| Does design meet metal density rules? | |
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2016-05-31 13:19:26 -04:00
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| Test | Answer |
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|--------------------------------------------|--------------------------------|
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| Does design use standard scan DFT? | |
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| What is the scan coverage? | |
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| What is the PPM defect ratio target? | |
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| Are ATPG vectors generated? | |
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| What fault models are used for vectors? | |
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| What are the end user quality requirements?| |
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| Are test ports controllable from pins? | |
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| What is the estimated test time? | |
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| Can all IO pins be tested for opens/short? | |
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| Does chip include temp sensor? | |
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| Circuit Checks | Answer |
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|--------------------------------------------|--------------------------------|
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| Does design pass Signal Integrity checks? | |
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| Does gate level design boot out of reset? | |
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| Does design meeet Electromigration rules? | |
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| Does design meet antenna rules? | |
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| Are metastability requirement met? | |
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| Are soft error rate requirements met? | |
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| Are on-chip decoupling caps sufficient? | |
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| Are on-package decoupling caps sufficient? | |
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| Are RC delays minimized? | |
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| Are all latchup requirements met? | |
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| Design's lowest operating voltage? | |
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| What is the longest signal on the chip? | |
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| Is design sensitive to duty cycle shift? | |
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2016-05-31 13:31:34 -04:00
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| What is the max duty-cycle distortion? | |
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| Does design meet EMI constraints? | |
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| ERC runset checks run on GDSII? | |
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2016-05-31 13:19:26 -04:00
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