2014-11-19 12:02:18 -05:00
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<?xml version="1.0" encoding="UTF-8"?>
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<spirit:component xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
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<spirit:vendor>adapteva.com</spirit:vendor>
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<spirit:library>Adapteva</spirit:library>
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<spirit:name>eclock</spirit:name>
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<spirit:version>1.0</spirit:version>
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<spirit:busInterfaces>
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<spirit:busInterface>
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<spirit:name>signal_reset</spirit:name>
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<spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset" spirit:version="1.0"/>
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<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset_rtl" spirit:version="1.0"/>
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<spirit:slave/>
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<spirit:portMap>
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<spirit:logicalPort>
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<spirit:name>RST</spirit:name>
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</spirit:logicalPort>
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<spirit:physicalPort>
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<spirit:name>reset</spirit:name>
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</spirit:physicalPort>
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</spirit:portMap>
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<spirit:parameters>
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<spirit:parameter>
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<spirit:name>POLARITY</spirit:name>
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<spirit:value spirit:format="string" spirit:resolve="immediate" spirit:id="BUSIFPARAM_VALUE.SIGNAL_RESET.POLARITY" spirit:choiceRef="choices_0">ACTIVE_HIGH</spirit:value>
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</spirit:parameter>
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<spirit:busInterface>
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<spirit:name>ecfg_cclk</spirit:name>
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<spirit:busType spirit:vendor="adapteva.com" spirit:library="Adapteva" spirit:name="eClockCfg" spirit:version="1.0"/>
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<spirit:abstractionType spirit:vendor="adapteva.com" spirit:library="Adapteva" spirit:name="eClockCfg_rtl" spirit:version="1.0"/>
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<spirit:slave/>
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<spirit:portMap>
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<spirit:logicalPort>
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<spirit:name>div</spirit:name>
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</spirit:logicalPort>
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<spirit:physicalPort>
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<spirit:name>ecfg_cclk_div</spirit:name>
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</spirit:physicalPort>
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</spirit:portMap>
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<spirit:portMap>
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<spirit:logicalPort>
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<spirit:name>pllcfg</spirit:name>
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</spirit:logicalPort>
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<spirit:physicalPort>
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<spirit:name>ecfg_cclk_pllcfg</spirit:name>
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</spirit:physicalPort>
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</spirit:portMap>
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<spirit:portMap>
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<spirit:logicalPort>
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<spirit:name>en</spirit:name>
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</spirit:logicalPort>
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<spirit:physicalPort>
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<spirit:name>ecfg_cclk_en</spirit:name>
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</spirit:physicalPort>
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</spirit:portMap>
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</spirit:busInterface>
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</spirit:busInterfaces>
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<spirit:model>
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<spirit:views>
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<spirit:view>
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<spirit:name>xilinx_verilogsynthesis</spirit:name>
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<spirit:displayName>Verilog Synthesis</spirit:displayName>
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<spirit:envIdentifier>verilogSource:vivado.xilinx.com:synthesis</spirit:envIdentifier>
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<spirit:language>verilog</spirit:language>
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<spirit:modelName>eclock</spirit:modelName>
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<spirit:fileSetRef>
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<spirit:localName>xilinx_verilogsynthesis_view_fileset</spirit:localName>
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</spirit:fileSetRef>
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<spirit:parameters>
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<spirit:parameter>
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<spirit:name>viewChecksum</spirit:name>
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<spirit:value>4c07ce39</spirit:value>
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</spirit:parameter>
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</spirit:parameters>
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</spirit:view>
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<spirit:view>
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<spirit:name>xilinx_verilogbehavioralsimulation</spirit:name>
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<spirit:displayName>Verilog Simulation</spirit:displayName>
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<spirit:envIdentifier>verilogSource:vivado.xilinx.com:simulation</spirit:envIdentifier>
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<spirit:language>verilog</spirit:language>
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<spirit:modelName>eclock</spirit:modelName>
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<spirit:fileSetRef>
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<spirit:localName>xilinx_verilogbehavioralsimulation_view_fileset</spirit:localName>
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</spirit:fileSetRef>
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<spirit:parameters>
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<spirit:parameter>
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<spirit:name>viewChecksum</spirit:name>
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<spirit:value>4c07ce39</spirit:value>
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</spirit:parameter>
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</spirit:parameters>
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</spirit:view>
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<spirit:view>
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<spirit:name>xilinx_xpgui</spirit:name>
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<spirit:displayName>UI Layout</spirit:displayName>
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<spirit:envIdentifier>:vivado.xilinx.com:xgui.ui</spirit:envIdentifier>
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<spirit:fileSetRef>
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<spirit:localName>xilinx_xpgui_view_fileset</spirit:localName>
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</spirit:fileSetRef>
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<spirit:parameters>
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<spirit:parameter>
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<spirit:name>viewChecksum</spirit:name>
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<spirit:value>f5b360c1</spirit:value>
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</spirit:parameter>
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</spirit:parameters>
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</spirit:view>
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</spirit:views>
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<spirit:ports>
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<spirit:port>
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<spirit:name>CCLK_P</spirit:name>
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<spirit:wire>
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<spirit:direction>out</spirit:direction>
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<spirit:wireTypeDefs>
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<spirit:wireTypeDef>
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<spirit:typeName>std_logic</spirit:typeName>
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<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
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<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
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</spirit:wireTypeDef>
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</spirit:wireTypeDefs>
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</spirit:wire>
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</spirit:port>
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<spirit:port>
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<spirit:name>CCLK_N</spirit:name>
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<spirit:wire>
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<spirit:direction>out</spirit:direction>
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<spirit:wireTypeDefs>
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<spirit:wireTypeDef>
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<spirit:typeName>std_logic</spirit:typeName>
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<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
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<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
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</spirit:wireTypeDef>
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</spirit:wireTypeDefs>
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</spirit:wire>
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</spirit:port>
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<spirit:port>
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<spirit:name>lclk_s</spirit:name>
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<spirit:wire>
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<spirit:direction>out</spirit:direction>
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<spirit:wireTypeDefs>
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<spirit:wireTypeDef>
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<spirit:typeName>std_logic</spirit:typeName>
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<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
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<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
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</spirit:wireTypeDef>
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</spirit:wireTypeDefs>
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</spirit:wire>
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</spirit:port>
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<spirit:port>
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<spirit:name>lclk_out</spirit:name>
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<spirit:wire>
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<spirit:direction>out</spirit:direction>
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<spirit:wireTypeDefs>
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<spirit:wireTypeDef>
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<spirit:typeName>std_logic</spirit:typeName>
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<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
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<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
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</spirit:wireTypeDef>
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</spirit:wireTypeDefs>
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</spirit:wire>
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</spirit:port>
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<spirit:port>
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<spirit:name>lclk_p</spirit:name>
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<spirit:wire>
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<spirit:direction>out</spirit:direction>
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<spirit:wireTypeDefs>
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<spirit:wireTypeDef>
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<spirit:typeName>std_logic</spirit:typeName>
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<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
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<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
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</spirit:wireTypeDef>
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</spirit:wireTypeDefs>
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</spirit:wire>
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</spirit:port>
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<spirit:port>
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<spirit:name>clkin</spirit:name>
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<spirit:wire>
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<spirit:direction>in</spirit:direction>
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<spirit:wireTypeDefs>
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<spirit:wireTypeDef>
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<spirit:typeName>std_logic</spirit:typeName>
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<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
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<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
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</spirit:wireTypeDef>
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</spirit:wireTypeDefs>
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</spirit:wire>
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</spirit:port>
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<spirit:port>
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<spirit:name>reset</spirit:name>
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<spirit:wire>
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<spirit:direction>in</spirit:direction>
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<spirit:wireTypeDefs>
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<spirit:wireTypeDef>
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<spirit:typeName>std_logic</spirit:typeName>
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<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
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<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
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</spirit:wireTypeDef>
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</spirit:wireTypeDefs>
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</spirit:wire>
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</spirit:port>
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<spirit:port>
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<spirit:name>ecfg_cclk_en</spirit:name>
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<spirit:wire>
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<spirit:direction>in</spirit:direction>
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<spirit:wireTypeDefs>
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<spirit:wireTypeDef>
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<spirit:typeName>std_logic</spirit:typeName>
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<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
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<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
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</spirit:wireTypeDef>
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</spirit:wireTypeDefs>
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</spirit:wire>
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</spirit:port>
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<spirit:port>
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<spirit:name>ecfg_cclk_div</spirit:name>
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<spirit:wire>
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<spirit:direction>in</spirit:direction>
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<spirit:vector>
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<spirit:left spirit:format="long" spirit:resolve="immediate">3</spirit:left>
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<spirit:right spirit:format="long" spirit:resolve="immediate">0</spirit:right>
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</spirit:vector>
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<spirit:wireTypeDefs>
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<spirit:wireTypeDef>
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<spirit:typeName>std_logic_vector</spirit:typeName>
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<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
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<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
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</spirit:wireTypeDef>
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</spirit:wireTypeDefs>
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</spirit:wire>
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</spirit:port>
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<spirit:port>
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<spirit:name>ecfg_cclk_pllcfg</spirit:name>
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<spirit:wire>
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<spirit:direction>in</spirit:direction>
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<spirit:vector>
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<spirit:left spirit:format="long" spirit:resolve="immediate">3</spirit:left>
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<spirit:right spirit:format="long" spirit:resolve="immediate">0</spirit:right>
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</spirit:vector>
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<spirit:wireTypeDefs>
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<spirit:wireTypeDef>
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<spirit:typeName>std_logic_vector</spirit:typeName>
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<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
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|
|
|
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<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
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</spirit:wireTypeDef>
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</spirit:wireTypeDefs>
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</spirit:wire>
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</spirit:port>
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</spirit:ports>
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<spirit:modelParameters>
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<spirit:modelParameter xsi:type="spirit:nameValueTypeType" spirit:dataType="integer">
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<spirit:name>CLKIN_PERIOD</spirit:name>
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<spirit:displayName>Clkin Period</spirit:displayName>
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<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.CLKIN_PERIOD">10</spirit:value>
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</spirit:modelParameter>
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<spirit:modelParameter spirit:dataType="integer">
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<spirit:name>CLKIN_DIVIDE</spirit:name>
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<spirit:displayName>Clkin Divide</spirit:displayName>
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<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.CLKIN_DIVIDE">1</spirit:value>
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</spirit:modelParameter>
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<spirit:modelParameter spirit:dataType="integer">
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<spirit:name>VCO_MULT</spirit:name>
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<spirit:displayName>Vco Mult</spirit:displayName>
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<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.VCO_MULT">12</spirit:value>
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</spirit:modelParameter>
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<spirit:modelParameter spirit:dataType="integer">
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<spirit:name>CCLK_DIVIDE</spirit:name>
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<spirit:displayName>Cclk Divide</spirit:displayName>
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<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.CCLK_DIVIDE">2</spirit:value>
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</spirit:modelParameter>
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<spirit:modelParameter spirit:dataType="integer">
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<spirit:name>LCLK_DIVIDE</spirit:name>
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<spirit:displayName>Lclk Divide</spirit:displayName>
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<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.LCLK_DIVIDE">4</spirit:value>
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</spirit:modelParameter>
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<spirit:modelParameter spirit:dataType="integer">
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<spirit:name>FEATURE_CCLK_DIV</spirit:name>
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<spirit:displayName>Feature Cclk Div</spirit:displayName>
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<spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.FEATURE_CCLK_DIV" spirit:bitStringLength="1">"1"</spirit:value>
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</spirit:modelParameter>
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<spirit:modelParameter spirit:dataType="string">
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<spirit:name>IOSTD_ELINK</spirit:name>
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<spirit:displayName>Iostd Elink</spirit:displayName>
|
|
|
|
|
<spirit:value spirit:format="string" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.IOSTD_ELINK">LVDS_25</spirit:value>
|
|
|
|
|
</spirit:modelParameter>
|
|
|
|
|
</spirit:modelParameters>
|
|
|
|
|
</spirit:model>
|
|
|
|
|
<spirit:choices>
|
|
|
|
|
<spirit:choice>
|
|
|
|
|
<spirit:name>choices_0</spirit:name>
|
|
|
|
|
<spirit:enumeration>ACTIVE_HIGH</spirit:enumeration>
|
|
|
|
|
<spirit:enumeration>ACTIVE_LOW</spirit:enumeration>
|
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|
</spirit:choice>
|
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|
</spirit:choices>
|
|
|
|
|
<spirit:fileSets>
|
|
|
|
|
<spirit:fileSet>
|
|
|
|
|
<spirit:name>xilinx_verilogsynthesis_view_fileset</spirit:name>
|
|
|
|
|
<spirit:file>
|
|
|
|
|
<spirit:name>hdl/eclock.v</spirit:name>
|
|
|
|
|
<spirit:fileType>verilogSource</spirit:fileType>
|
2014-11-24 01:57:57 -05:00
|
|
|
<spirit:userFileType>CHECKSUM_e391c4dc</spirit:userFileType>
|
2014-11-19 12:02:18 -05:00
|
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|
</spirit:file>
|
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|
|
|
</spirit:fileSet>
|
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|
|
<spirit:fileSet>
|
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|
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|
<spirit:name>xilinx_verilogbehavioralsimulation_view_fileset</spirit:name>
|
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<spirit:file>
|
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|
|
|
<spirit:name>hdl/eclock.v</spirit:name>
|
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|
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|
<spirit:fileType>verilogSource</spirit:fileType>
|
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|
</spirit:file>
|
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|
|
|
</spirit:fileSet>
|
|
|
|
|
<spirit:fileSet>
|
|
|
|
|
<spirit:name>xilinx_xpgui_view_fileset</spirit:name>
|
|
|
|
|
<spirit:file>
|
|
|
|
|
<spirit:name>xgui/eclock_v1_0.tcl</spirit:name>
|
|
|
|
|
<spirit:fileType>tclSource</spirit:fileType>
|
|
|
|
|
<spirit:userFileType>XGUI_VERSION_2</spirit:userFileType>
|
|
|
|
|
<spirit:userFileType>CHECKSUM_f5b360c1</spirit:userFileType>
|
|
|
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|
</spirit:file>
|
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|
|
|
</spirit:fileSet>
|
|
|
|
|
</spirit:fileSets>
|
|
|
|
|
<spirit:description>eClock Clock Generation Module</spirit:description>
|
|
|
|
|
<spirit:parameters>
|
|
|
|
|
<spirit:parameter>
|
|
|
|
|
<spirit:name>IOSTD_ELINK</spirit:name>
|
|
|
|
|
<spirit:displayName>Iostd Elink</spirit:displayName>
|
|
|
|
|
<spirit:value spirit:format="string" spirit:resolve="user" spirit:id="PARAM_VALUE.IOSTD_ELINK" spirit:order="1100">LVDS_25</spirit:value>
|
|
|
|
|
</spirit:parameter>
|
|
|
|
|
<spirit:parameter>
|
|
|
|
|
<spirit:name>FEATURE_CCLK_DIV</spirit:name>
|
|
|
|
|
<spirit:displayName>Feature Cclk Div</spirit:displayName>
|
|
|
|
|
<spirit:value spirit:format="bitString" spirit:resolve="user" spirit:id="PARAM_VALUE.FEATURE_CCLK_DIV" spirit:order="1200" spirit:bitStringLength="1">"1"</spirit:value>
|
|
|
|
|
</spirit:parameter>
|
|
|
|
|
<spirit:parameter>
|
|
|
|
|
<spirit:name>LCLK_DIVIDE</spirit:name>
|
|
|
|
|
<spirit:displayName>Lclk Divide</spirit:displayName>
|
|
|
|
|
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.LCLK_DIVIDE" spirit:order="1300">4</spirit:value>
|
|
|
|
|
</spirit:parameter>
|
|
|
|
|
<spirit:parameter>
|
|
|
|
|
<spirit:name>CCLK_DIVIDE</spirit:name>
|
|
|
|
|
<spirit:displayName>Cclk Divide</spirit:displayName>
|
|
|
|
|
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.CCLK_DIVIDE" spirit:order="1400">2</spirit:value>
|
|
|
|
|
</spirit:parameter>
|
|
|
|
|
<spirit:parameter>
|
|
|
|
|
<spirit:name>VCO_MULT</spirit:name>
|
|
|
|
|
<spirit:displayName>Vco Mult</spirit:displayName>
|
|
|
|
|
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.VCO_MULT" spirit:order="1500">12</spirit:value>
|
|
|
|
|
</spirit:parameter>
|
|
|
|
|
<spirit:parameter>
|
|
|
|
|
<spirit:name>CLKIN_DIVIDE</spirit:name>
|
|
|
|
|
<spirit:displayName>Clkin Divide</spirit:displayName>
|
|
|
|
|
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.CLKIN_DIVIDE" spirit:order="1600">1</spirit:value>
|
|
|
|
|
</spirit:parameter>
|
|
|
|
|
<spirit:parameter>
|
|
|
|
|
<spirit:name>CLKIN_PERIOD</spirit:name>
|
|
|
|
|
<spirit:displayName>Clkin Period</spirit:displayName>
|
|
|
|
|
<spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.CLKIN_PERIOD" spirit:order="1700" spirit:configGroups="0 UnGrouped textEdit">10</spirit:value>
|
|
|
|
|
</spirit:parameter>
|
|
|
|
|
<spirit:parameter>
|
|
|
|
|
<spirit:name>Component_Name</spirit:name>
|
|
|
|
|
<spirit:displayName>Component Name</spirit:displayName>
|
|
|
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Component_Name" spirit:order="1">eclock_v1_0</spirit:value>
|
|
|
|
|
</spirit:parameter>
|
|
|
|
|
</spirit:parameters>
|
|
|
|
|
<spirit:vendorExtensions>
|
|
|
|
|
<xilinx:coreExtensions>
|
|
|
|
|
<xilinx:supportedFamilies>
|
|
|
|
|
<xilinx:family xilinx:lifeCycle="Pre-Production">zynq</xilinx:family>
|
|
|
|
|
</xilinx:supportedFamilies>
|
|
|
|
|
<xilinx:taxonomies>
|
|
|
|
|
<xilinx:taxonomy>/BaseIP</xilinx:taxonomy>
|
|
|
|
|
</xilinx:taxonomies>
|
|
|
|
|
<xilinx:displayName>eclock_v1_0</xilinx:displayName>
|
2014-11-24 01:57:57 -05:00
|
|
|
<xilinx:vendorDisplayName>Adapteva, Inc.</xilinx:vendorDisplayName>
|
2014-11-19 12:02:18 -05:00
|
|
|
<xilinx:vendorURL>http://www.adapteva.com</xilinx:vendorURL>
|
2014-11-24 01:57:57 -05:00
|
|
|
<xilinx:coreRevision>7</xilinx:coreRevision>
|
|
|
|
|
<xilinx:coreCreationDateTime>2014-11-21T16:37:07Z</xilinx:coreCreationDateTime>
|
2014-11-19 12:02:18 -05:00
|
|
|
<xilinx:tags>
|
|
|
|
|
<xilinx:tag xilinx:name="user.org:user:eclock:1.0_ARCHIVE_LOCATION">/mnt/windowsC/Adapteva/Parallella/parallella-hwelink/fpga/hdl/eclock/ip</xilinx:tag>
|
|
|
|
|
<xilinx:tag xilinx:name="adapteva.com:user:eclock:1.0_ARCHIVE_LOCATION">/mnt/windowsC/Adapteva/Parallella/parallella-hwelink/fpga/hdl/eclock/ip</xilinx:tag>
|
2014-11-24 01:57:57 -05:00
|
|
|
<xilinx:tag xilinx:name="adapteva.com:Adapteva:eclock:1.0_ARCHIVE_LOCATION">/home/frhuettig</xilinx:tag>
|
2014-11-19 12:02:18 -05:00
|
|
|
</xilinx:tags>
|
|
|
|
|
</xilinx:coreExtensions>
|
|
|
|
|
<xilinx:packagingInfo>
|
|
|
|
|
<xilinx:xilinxVersion>2014.3</xilinx:xilinxVersion>
|
|
|
|
|
<xilinx:checksum xilinx:scope="busInterfaces" xilinx:value="e77f0e30"/>
|
|
|
|
|
<xilinx:checksum xilinx:scope="fileGroups" xilinx:value="d6cf9a4d"/>
|
|
|
|
|
<xilinx:checksum xilinx:scope="ports" xilinx:value="abdeedc3"/>
|
|
|
|
|
<xilinx:checksum xilinx:scope="hdlParameters" xilinx:value="b5e7f9c5"/>
|
|
|
|
|
<xilinx:checksum xilinx:scope="parameters" xilinx:value="265acca5"/>
|
|
|
|
|
</xilinx:packagingInfo>
|
|
|
|
|
</spirit:vendorExtensions>
|
|
|
|
|
</spirit:component>
|
