oh/elink/fpga/axi_elink_timing.xdc

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#SYS_CLK
create_clock -name sys_clk -period 10 [get_ports sys_clk]

#RECEIVER
create_clock -period 3.333 -name rx_lclk -waveform {0.000 1.667} [get_ports rxi_lclk_p]
Adding timing constraints - structure feels right - one folder per reusable module - everything should be contained within one "package" 2015-11-04 22:13:35 -05:00			`#SYS_CLK`
			`create_clock -name sys_clk -period 10 [get_ports sys_clk]`

			`#RECEIVER`
			`create_clock -period 3.333 -name rx_lclk -waveform {0.000 1.667} [get_ports rxi_lclk_p]`