oh/scripts/build.sh

#!/bin/bash

############################################################################
# Icarus Verilog build script for OH! 
#
# Requires $OH_HOME variable to be set
#
# Example: ./scripts/build.sh elink/hdl/dut_elink.v
#
############################################################################

##############################
#Build
###############################
iverilog -g2005\
 -DTARGET_SIM=1\
 -DCFG_ASIC=0\
 -f $OH_HOME/scripts/libs.cmd \
 -o dut.bin $1
Putting simplified scripts in $OH_HOME 2016-03-08 15:49:15 -05:00			`#!/bin/bash`

			`############################################################################`
			`# Icarus Verilog build script for OH!`
Reorg cleanup 2016-03-22 08:27:59 -04:00			`#`
Putting simplified scripts in $OH_HOME 2016-03-08 15:49:15 -05:00			`# Requires $OH_HOME variable to be set`
Reorg cleanup 2016-03-22 08:27:59 -04:00			`#`
			`# Example: ./scripts/build.sh elink/hdl/dut_elink.v`
			`#`
Putting simplified scripts in $OH_HOME 2016-03-08 15:49:15 -05:00			`############################################################################`

			`##############################`
			`#Build`
			`###############################`
			`iverilog -g2005\`
			`-DTARGET_SIM=1\`
Making CFG_ASIC a primary variable -Need to separate between open FPGA design and closed ASIC design. -NDAs means it's imposssible for us to disclose even the interfaces of the cells inside without taking the risk of violating the terms of the NDA. -For this reason, we come up with generic and clean asic library interfaces that need to be implemented in each library/technology 2016-06-19 17:05:50 -04:00			`-DCFG_ASIC=0\`
Major reorg! -stdcells moved to asiclib, doesn't make sense to be vectorized -common is a stupid name, renamed as stdlib 2021-07-29 11:20:44 -04:00			`-f $OH_HOME/scripts/libs.cmd \`
			`-o dut.bin $1`