oh/stdlib/testbench/run.sh

#!/bin/bash

#ARGUMENTS
#$1=name of "dut*.bin" to simulate
#$2=path to test to run

#Uses BASH $RANDOM variable to set seed

rm test_0.emf
ln -s $2 test_0.emf
./$1 +SEED=$RANDOM
Adding missing files 2015-11-03 14:16:50 -05:00			`#!/bin/bash`
Adding clk90 output to clkdiv -Added testbench -Needs more review! 2016-02-23 17:49:08 -05:00
Adding "SEED" as basic parameter -making randomness clocks a first class citizen -Verilog doesn't have a seed, need to drive it from the shell -a must for async clocks, useful for many things -does not preclude randomization externally as well 2016-02-24 14:21:04 -05:00			`#ARGUMENTS`
			`#$1=name of "dut*.bin" to simulate`
			`#$2=path to test to run`

			`#Uses BASH $RANDOM variable to set seed`

Adding clk90 output to clkdiv -Added testbench -Needs more review! 2016-02-23 17:49:08 -05:00			`rm test_0.emf`
			`ln -s $2 test_0.emf`
Adding "SEED" as basic parameter -making randomness clocks a first class citizen -Verilog doesn't have a seed, need to drive it from the shell -a must for async clocks, useful for many things -does not preclude randomization externally as well 2016-02-24 14:21:04 -05:00			`./$1 +SEED=$RANDOM`