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oh/elink/hdl/eclocks.v

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Continued work to create clean design: -pll bypass for clocks (customer request) -adding dividers on all clocks (tx/cclk) -adding reset block (clearer) -using commong clock_divider block -need to clean up divider block later today, slightly broken:-)
2015-04-15 11:54:43 -04:00
/*###########################################################################
Cleaning up clocks -moving to "real" Xilinx PLL instantiation -one PLL for CCLK one for LCLK -removing clock dividers, can't work at speed, put inside model -configuration needs to be done differently -removing pll_bypass signal, can't work with logic -clocks should be done with hard macro primitives (no logic)
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# Function: Clock generator for elink
Continued work to create clean design: -pll bypass for clocks (customer request) -adding dividers on all clocks (tx/cclk) -adding reset block (clearer) -using commong clock_divider block -need to clean up divider block later today, slightly broken:-)
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#
Clarified lclk names
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# cclk_p/n - Epiphany Output Clock (>600MHz)
Continued work to create clean design: -pll bypass for clocks (customer request) -adding dividers on all clocks (tx/cclk) -adding reset block (clearer) -using commong clock_divider block -need to clean up divider block later today, slightly broken:-)
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#
Clarified lclk names
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# tx_lclk_div4 - Parallel data clock (125Mhz)
Continued work to create clean design: -pll bypass for clocks (customer request) -adding dividers on all clocks (tx/cclk) -adding reset block (clearer) -using commong clock_divider block -need to clean up divider block later today, slightly broken:-)
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#
Clarified lclk names
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# tx_lclk - Serial DDR data clock (500MHz)
Continued work to create clean design: -pll bypass for clocks (customer request) -adding dividers on all clocks (tx/cclk) -adding reset block (clearer) -using commong clock_divider block -need to clean up divider block later today, slightly broken:-)
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#
Clarified lclk names
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# tx_lclk90 - DDR "Clock" clock, to generate tx_lclk_p/n output
# Same as lclk, shifted by 90 degrees
Continued work to create clean design: -pll bypass for clocks (customer request) -adding dividers on all clocks (tx/cclk) -adding reset block (clearer) -using commong clock_divider block -need to clean up divider block later today, slightly broken:-)
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#
############################################################################
*/
module eclocks (/*AUTOARG*/
// Outputs
Clarified lclk names
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cclk_p, cclk_n, tx_lclk, tx_lclk90, tx_lclk_div4,
Continued work to create clean design: -pll bypass for clocks (customer request) -adding dividers on all clocks (tx/cclk) -adding reset block (clearer) -using commong clock_divider block -need to clean up divider block later today, slightly broken:-)
2015-04-15 11:54:43 -04:00
// Inputs
Cleaning up clocks -moving to "real" Xilinx PLL instantiation -one PLL for CCLK one for LCLK -removing clock dividers, can't work at speed, put inside model -configuration needs to be done differently -removing pll_bypass signal, can't work with logic -clocks should be done with hard macro primitives (no logic)
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hard_reset, pll_clkin
Continued work to create clean design: -pll bypass for clocks (customer request) -adding dividers on all clocks (tx/cclk) -adding reset block (clearer) -using commong clock_divider block -need to clean up divider block later today, slightly broken:-)
2015-04-15 11:54:43 -04:00
);
Cleaning up clocks -moving to "real" Xilinx PLL instantiation -one PLL for CCLK one for LCLK -removing clock dividers, can't work at speed, put inside model -configuration needs to be done differently -removing pll_bypass signal, can't work with logic -clocks should be done with hard macro primitives (no logic)
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parameter CLKIN_PERIOD = 10.000; // (2.5-100ns, set by system)
// must match actual sytem clock
//
Continued work to create clean design: -pll bypass for clocks (customer request) -adding dividers on all clocks (tx/cclk) -adding reset block (clearer) -using commong clock_divider block -need to clean up divider block later today, slightly broken:-)
2015-04-15 11:54:43 -04:00
//Input clock, reset, config interface
Cleaning up clocks -moving to "real" Xilinx PLL instantiation -one PLL for CCLK one for LCLK -removing clock dividers, can't work at speed, put inside model -configuration needs to be done differently -removing pll_bypass signal, can't work with logic -clocks should be done with hard macro primitives (no logic)
2015-05-06 12:23:15 -04:00
input hard_reset; // hardware reset
input pll_clkin; // primary input clock
//outputs
Continued work to create clean design: -pll bypass for clocks (customer request) -adding dividers on all clocks (tx/cclk) -adding reset block (clearer) -using commong clock_divider block -need to clean up divider block later today, slightly broken:-)
2015-04-15 11:54:43 -04:00
output cclk_p, cclk_n; // high speed Epiphany clock (up to 1GHz)
output tx_lclk; // elink tx serdes clock
Clarified lclk names
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output tx_lclk90; // center aligned output clock for elink tx
output tx_lclk_div4; // lclk/4 slow clock for tx parallel logic
Continued work to create clean design: -pll bypass for clocks (customer request) -adding dividers on all clocks (tx/cclk) -adding reset block (clearer) -using commong clock_divider block -need to clean up divider block later today, slightly broken:-)
2015-04-15 11:54:43 -04:00
// Wires
Cleaning up clocks -moving to "real" Xilinx PLL instantiation -one PLL for CCLK one for LCLK -removing clock dividers, can't work at speed, put inside model -configuration needs to be done differently -removing pll_bypass signal, can't work with logic -clocks should be done with hard macro primitives (no logic)
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wire cclk_clkfb;
wire lclk_clkfb;
MILESTONE: Read/write works back and forth -Pipeline looks good, now need to test clk1>>clk2 and clk2>clk1 -Still not completely happy with reset (using async for now)
2015-05-04 17:13:51 -04:00
Cleaning up clocks -moving to "real" Xilinx PLL instantiation -one PLL for CCLK one for LCLK -removing clock dividers, can't work at speed, put inside model -configuration needs to be done differently -removing pll_bypass signal, can't work with logic -clocks should be done with hard macro primitives (no logic)
2015-05-06 12:23:15 -04:00
Clarified lclk names
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`ifdef TARGET_XILINX
Continued work to create clean design: -pll bypass for clocks (customer request) -adding dividers on all clocks (tx/cclk) -adding reset block (clearer) -using commong clock_divider block -need to clean up divider block later today, slightly broken:-)
2015-04-15 11:54:43 -04:00
Cleaning up clocks -moving to "real" Xilinx PLL instantiation -one PLL for CCLK one for LCLK -removing clock dividers, can't work at speed, put inside model -configuration needs to be done differently -removing pll_bypass signal, can't work with logic -clocks should be done with hard macro primitives (no logic)
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//###########################
// MMCM/PLL FOR CCLK
//###########################
parameter CCLK_VCO_MULT =12;
parameter CCLK_DIVIDE = 2;
PLLE2_BASE
#(
.BANDWIDTH("OPTIMIZED"),
.CLKFBOUT_MULT(CCLK_VCO_MULT),
.CLKFBOUT_PHASE(0.0),
.CLKIN1_PERIOD(CLKIN_PERIOD),
.CLKOUT0_DIVIDE(CCLK_DIVIDE), // cclk
.CLKOUT1_DIVIDE(CCLK_DIVIDE*2), // cclk/2
.CLKOUT2_DIVIDE(CCLK_DIVIDE*4), // cclk/4
.CLKOUT3_DIVIDE(CCLK_DIVIDE*8), // cclk/8
.CLKOUT4_DIVIDE(CCLK_DIVIDE*16), // cclk/16
.CLKOUT5_DIVIDE(CCLK_DIVIDE*32), // cclk/32
.CLKOUT0_DUTY_CYCLE(0.5),
.CLKOUT1_DUTY_CYCLE(0.5),
.CLKOUT2_DUTY_CYCLE(0.5),
.CLKOUT3_DUTY_CYCLE(0.5),
.CLKOUT4_DUTY_CYCLE(0.5),
.CLKOUT5_DUTY_CYCLE(0.5),
.CLKOUT0_PHASE(0.0),
.CLKOUT1_PHASE(0.0),
.CLKOUT2_PHASE(0.0),
.CLKOUT3_PHASE(0.0),
.CLKOUT4_PHASE(0.0),
.CLKOUT5_PHASE(0.0),
.DIVCLK_DIVIDE(1.0),
.REF_JITTER1(0.01),
.STARTUP_WAIT("FALSE")
) pll_cclk
(
.CLKOUT0(cclk),
.CLKOUT1(),
.CLKOUT2(),
.CLKOUT3(),
.CLKOUT4(),
.CLKOUT5(),
.CLKFBOUT(cclk_clkfb),
.LOCKED(),
.CLKIN1(pll_clkin),
.PWRDWN(1'b0),
.RST(1'b0),
.CLKFBIN(cclk_clkfb)
);
//###########################
// MMCM/PLL FOR LCLK
//###########################
parameter LCLK_VCO_MULT =10;
parameter LCLK_DIVIDE = 2;
PLLE2_BASE
#(
.BANDWIDTH("OPTIMIZED"),
.CLKFBOUT_MULT(LCLK_VCO_MULT),
.CLKFBOUT_PHASE(0.0),
.CLKIN1_PERIOD(CLKIN_PERIOD),
.CLKOUT0_DIVIDE(LCLK_DIVIDE), // lclk
.CLKOUT1_DIVIDE(LCLK_DIVIDE), // lclk90
.CLKOUT2_DIVIDE(LCLK_DIVIDE*4), // lclkdiv4
.CLKOUT3_DIVIDE(LCLK_DIVIDE*4), // lclk/4
.CLKOUT4_DIVIDE(LCLK_DIVIDE*4), // lclk/4 with 90 deg
.CLKOUT5_DIVIDE(LCLK_DIVIDE*16), // lclk/4-->div4
.CLKOUT0_DUTY_CYCLE(0.5),
.CLKOUT1_DUTY_CYCLE(0.5),
.CLKOUT2_DUTY_CYCLE(0.5),
.CLKOUT3_DUTY_CYCLE(0.5),
.CLKOUT4_DUTY_CYCLE(0.5),
.CLKOUT5_DUTY_CYCLE(0.5),
.CLKOUT0_PHASE(0.0),
.CLKOUT1_PHASE(90.0), // tx_lclk90 shifted by 90 degrees
.CLKOUT2_PHASE(0.0),
.CLKOUT3_PHASE(0.0),
.CLKOUT4_PHASE(90.0), //slow mode shifted by 90 degrees
.CLKOUT5_PHASE(0.0),
.DIVCLK_DIVIDE(1.0),
.REF_JITTER1(0.01),
.STARTUP_WAIT("FALSE")
) pll_lclk
(
.CLKOUT0(tx_lclk), //tx_lclk
.CLKOUT1(tx_lclk90), //tx_lclk90
.CLKOUT2(tx_lclk_div4), //tx_lclk_div4
.CLKOUT3(),
.CLKOUT4(),
.CLKOUT5(),
.CLKFBOUT(lclk_clkfb),
.LOCKED(),
.CLKIN1(pll_clkin),
.PWRDWN(1'b0),
.RST(1'b0),
.CLKFBIN(lclk_clkfb)
);
Adding clock buffer
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OBUFDS cclk_obuf (.O (cclk_p),
.OB (cclk_n),
.I (cclk)
);
Cleaning up clocks -moving to "real" Xilinx PLL instantiation -one PLL for CCLK one for LCLK -removing clock dividers, can't work at speed, put inside model -configuration needs to be done differently -removing pll_bypass signal, can't work with logic -clocks should be done with hard macro primitives (no logic)
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`endif // `ifdef TARGET_XILINX
/*
Continued work to create clean design: -pll bypass for clocks (customer request) -adding dividers on all clocks (tx/cclk) -adding reset block (clearer) -using commong clock_divider block -need to clean up divider block later today, slightly broken:-)
2015-04-15 11:54:43 -04:00
`elsif TARGET_CLEAN
Clarified lclk names
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Continued work to create clean design: -pll bypass for clocks (customer request) -adding dividers on all clocks (tx/cclk) -adding reset block (clearer) -using commong clock_divider block -need to clean up divider block later today, slightly broken:-)
2015-04-15 11:54:43 -04:00
clock_divider cclk_divider(
// Outputs
.clkout (cclk),
.clkout90 (),
// Inputs
Organization changes -dma with packet format -using the fifo_cdc block
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.clkin (clkin),
Verilator based lint cleanup
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.reset (hard_reset),
MILESTONE: Read/write works back and forth -Pipeline looks good, now need to test clk1>>clk2 and clk2>clk1 -Still not completely happy with reset (using async for now)
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.divcfg (clk_config[7:4])
)
;
Continued work to create clean design: -pll bypass for clocks (customer request) -adding dividers on all clocks (tx/cclk) -adding reset block (clearer) -using commong clock_divider block -need to clean up divider block later today, slightly broken:-)
2015-04-15 11:54:43 -04:00
clock_divider lclk_divider(
// Outputs
MILESTONE: Read/write works back and forth -Pipeline looks good, now need to test clk1>>clk2 and clk2>clk1 -Still not completely happy with reset (using async for now)
2015-05-04 17:13:51 -04:00
.clkout (lclk),
.clkout90 (lclk90),
Continued work to create clean design: -pll bypass for clocks (customer request) -adding dividers on all clocks (tx/cclk) -adding reset block (clearer) -using commong clock_divider block -need to clean up divider block later today, slightly broken:-)
2015-04-15 11:54:43 -04:00
// Inputs
Organization changes -dma with packet format -using the fifo_cdc block
2015-05-03 23:29:32 -04:00
.clkin (clkin),
Verilator based lint cleanup
2015-04-23 18:57:55 -04:00
.reset (hard_reset),
MILESTONE: Read/write works back and forth -Pipeline looks good, now need to test clk1>>clk2 and clk2>clk1 -Still not completely happy with reset (using async for now)
2015-05-04 17:13:51 -04:00
.divcfg (clk_config[11:8])
Continued work to create clean design: -pll bypass for clocks (customer request) -adding dividers on all clocks (tx/cclk) -adding reset block (clearer) -using commong clock_divider block -need to clean up divider block later today, slightly broken:-)
2015-04-15 11:54:43 -04:00
);
Clock/reset fixes -Making reset async -lclk_div4 always on (makes reset safer, not a big loss) -filtering non-matching transactions
2015-05-02 22:42:33 -04:00
//This clock is always on!
Continued work to create clean design: -pll bypass for clocks (customer request) -adding dividers on all clocks (tx/cclk) -adding reset block (clearer) -using commong clock_divider block -need to clean up divider block later today, slightly broken:-)
2015-04-15 11:54:43 -04:00
clock_divider lclk_par_divider(
// Outputs
MILESTONE: Read/write works back and forth -Pipeline looks good, now need to test clk1>>clk2 and clk2>clk1 -Still not completely happy with reset (using async for now)
2015-05-04 17:13:51 -04:00
.clkout (lclk_div4),
Fixed clock divider circuit -changed ecfg clock default values, elink default is now the PLL clock/128 coming out of reset -should work in any implementation? -still have to implement the Xilinx specific stuff
2015-04-15 14:56:29 -04:00
.clkout90 (),
Continued work to create clean design: -pll bypass for clocks (customer request) -adding dividers on all clocks (tx/cclk) -adding reset block (clearer) -using commong clock_divider block -need to clean up divider block later today, slightly broken:-)
2015-04-15 11:54:43 -04:00
// Inputs
Clock/reset fixes -Making reset async -lclk_div4 always on (makes reset safer, not a big loss) -filtering non-matching transactions
2015-05-02 22:42:33 -04:00
.clkin (clkin),
Verilator based lint cleanup
2015-04-23 18:57:55 -04:00
.reset (hard_reset),
MILESTONE: Read/write works back and forth -Pipeline looks good, now need to test clk1>>clk2 and clk2>clk1 -Still not completely happy with reset (using async for now)
2015-05-04 17:13:51 -04:00
.divcfg (clk_config[11:8] + 4'd2)
Continued work to create clean design: -pll bypass for clocks (customer request) -adding dividers on all clocks (tx/cclk) -adding reset block (clearer) -using commong clock_divider block -need to clean up divider block later today, slightly broken:-)
2015-04-15 11:54:43 -04:00
);
MILESTONE: Read/write works back and forth -Pipeline looks good, now need to test clk1>>clk2 and clk2>clk1 -Still not completely happy with reset (using async for now)
2015-05-04 17:13:51 -04:00
//cclk (hack for sim)
Adding clock buffer
2015-05-07 23:44:39 -04:00
MILESTONE: Read/write works back and forth -Pipeline looks good, now need to test clk1>>clk2 and clk2>clk1 -Still not completely happy with reset (using async for now)
2015-05-04 17:13:51 -04:00
//lclk (hack for sim)
assign tx_lclk = hard_reset ? clkin :
lclk_bp ? pll_bypass[1] :
lclk;
assign tx_lclk90 = hard_reset ? clkin :
lclk_bp ? pll_bypass[2] :
lclk90;
assign tx_lclk_div4 = hard_reset ? clkin :
lclk_bp ? pll_bypass[3] :
lclk_div4;
Clarified lclk names
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Continued work to create clean design: -pll bypass for clocks (customer request) -adding dividers on all clocks (tx/cclk) -adding reset block (clearer) -using commong clock_divider block -need to clean up divider block later today, slightly broken:-)
2015-04-15 11:54:43 -04:00
`endif
Cleaning up clocks -moving to "real" Xilinx PLL instantiation -one PLL for CCLK one for LCLK -removing clock dividers, can't work at speed, put inside model -configuration needs to be done differently -removing pll_bypass signal, can't work with logic -clocks should be done with hard macro primitives (no logic)
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reg clkint;
initial
begin
clkint=1'b0;
end
always
#0.5 clkint = ~clkint;
*/
Continued work to create clean design: -pll bypass for clocks (customer request) -adding dividers on all clocks (tx/cclk) -adding reset block (clearer) -using commong clock_divider block -need to clean up divider block later today, slightly broken:-)
2015-04-15 11:54:43 -04:00
endmodule // eclocks
// Local Variables:
// verilog-library-directories:("." "../../common/hdl")
// End:
/*
Copyright (C) 2014 Adapteva, Inc.
Clarified lclk names
2015-04-22 15:03:24 -04:00
Contributed by Andreas Olofsson <andreas@adapteva.com>
Continued work to create clean design: -pll bypass for clocks (customer request) -adding dividers on all clocks (tx/cclk) -adding reset block (clearer) -using commong clock_divider block -need to clean up divider block later today, slightly broken:-)
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This program is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.This program is distributed in the hope
that it will be useful,but WITHOUT ANY WARRANTY without even the implied
warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details. You should have received a copy
of the GNU General Public License along with this program (see the file
COPYING). If not, see <http://www.gnu.org/licenses/>.
*/
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