2015-04-21 21:22:30 -04:00
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=======
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2015-04-21 21:19:10 -04:00
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# OH!
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2015-04-21 21:36:37 -04:00
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2015-11-06 11:31:16 -05:00
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An Open Hardware Library for Chip and FPGA designers written in Verilog
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2015-11-01 16:47:40 -05:00
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2015-11-06 11:31:16 -05:00
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## CONTENT
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2015-11-06 11:31:16 -05:00
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| Spec | Description |
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|---------------------|---------------------------------------------|
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| [common](common) | Common utility modules and scripts |
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| [edma](edma) | DMA module |
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| [emesh](emesh) | Epiphany emesh related circuits |
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| [elink](elink) | Epiphany point to point LVDS link |
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| [emailbox](emailbox)| Simple mailbox with interrupt output |
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| [emmu](emmu) | Simple memory transaction translation unit |
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| [memory](memory) | Various simple memory structures (RAM/FIFO) |
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| [xilibs](xilibs) | Simulation modules for Xilinx primitives |
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2015-07-05 23:32:28 +02:00
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2015-11-03 10:46:05 -05:00
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## LICENSE
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2015-11-06 11:25:05 -05:00
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The OH! repository source code is licensed under the MIT license unless otherwise specified. See [LICENSE](LICENSE) for full copyright terms.
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2015-11-01 17:09:12 -05:00
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2015-11-06 11:31:16 -05:00
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## CONTRIBUTING
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Instructions for contributing can be found [HERE](CONTRIBUTING.md).
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