oh/elink/dv/elink.cmd

../hdl/elink_constants.v
../hdl/elink_regmap.v
dv_elink_tb.v
elink_e16_model.v
-y .
-y ../../elink/hdl
-y ../../xilibs/hdl
-y ../../common/hdl
-y ../../memory/hdl
-y ../../emailbox/hdl
-y ../../emesh/hdl
-y ../../emmu/hdl
-y ../../edma/hdl
Cleanup 2015-04-22 13:56:29 -04:00			`../hdl/elink_constants.v`
Reorg 2015-04-21 21:33:49 -04:00			`../hdl/elink_regmap.v`
Verilator lint cleanup ~10 real bugs -mostly name mismatches and bit range mistakes 2015-04-14 14:00:23 -04:00			`dv_elink_tb.v`
Adding e16 elink golden reference to dv environment 2015-05-01 17:32:52 -04:00			`elink_e16_model.v`
Fixing typo 2015-03-23 15:46:56 -04:00			`-y .`
			`-y ../../elink/hdl`
Cleanup 2015-04-22 13:56:29 -04:00			`-y ../../xilibs/hdl`
Adding fofo environment for elink to check for broken signals. Too many stub modules to be practical..next need sim models 2014-12-14 22:17:23 -05:00			`-y ../../common/hdl`
			`-y ../../memory/hdl`
Packet interface changes 2015-04-23 18:09:16 -04:00			`-y ../../emailbox/hdl`
Adding emesh as basic building block 2015-05-05 21:38:41 -04:00			`-y ../../emesh/hdl`
Adding fofo environment for elink to check for broken signals. Too many stub modules to be practical..next need sim models 2014-12-14 22:17:23 -05:00			`-y ../../emmu/hdl`
Packet interface changes 2015-04-23 18:09:16 -04:00			`-y ../../edma/hdl`
Cleanup 2015-04-22 13:56:29 -04:00
Verilator inspired bug fixes -address width in elink -bus widths in ecfg -command file more generic 2014-12-15 15:25:09 -05:00