oh/elink/dv/run.sh

#!/bin/bash

#Linting in Verilator
#verilator --lint-only -F elink.cmd -DTARGET_VERILATOR dv_elink.v

#a sorry hack, too tired to get it right, please fix...
TRANS=$(wc -l test.memh)
TRANS=${TRANS:0:3}
#RANDOM TEST
iverilog -I../hdl -I../../emailbox/hdl -f elink.cmd -DMANUAL -DTRANS=$TRANS -DTESTNAME=test.memh -DTARGET_XILINX -DSIM
#iverilog -f elink.cmd -DAUTO

#Running sim
./a.out
Adding fofo environment for elink to check for broken signals. Too many stub modules to be practical..next need sim models 2014-12-14 22:17:23 -05:00			`#!/bin/bash`
Major cleanup, refactoring, and feature completion -adding clock bypass mode for esystx[12] -removing monitor feature on erx -remove loopback support from doc -add clock bypass mode for esysclk -shortening register names (descriptive enough) -added debug signal information -moving registers to elink -making elink version programmable (to support plug in boards) -reorganized debug signals and added stickys -added timeout for axi slave -removed embox status bit (redudant, don't poll status) -renamed EMBOX0-->EMBOXLO -moved datain interface straight to ecfg (cleanup) -changed etx arbiter priority to increase stability -created the esaxi_mux block -fixed some missing ports issues in stubs Now comes the fun part...verification... Andreas 2015-04-11 00:04:18 -04:00
			`#Linting in Verilator`
Broken testbench connections 2015-04-23 20:04:03 -04:00			`#verilator --lint-only -F elink.cmd -DTARGET_VERILATOR dv_elink.v`
Major cleanup, refactoring, and feature completion -adding clock bypass mode for esystx[12] -removing monitor feature on erx -remove loopback support from doc -add clock bypass mode for esysclk -shortening register names (descriptive enough) -added debug signal information -moving registers to elink -making elink version programmable (to support plug in boards) -reorganized debug signals and added stickys -added timeout for axi slave -removed embox status bit (redudant, don't poll status) -renamed EMBOX0-->EMBOXLO -moved datain interface straight to ecfg (cleanup) -changed etx arbiter priority to increase stability -created the esaxi_mux block -fixed some missing ports issues in stubs Now comes the fun part...verification... Andreas 2015-04-11 00:04:18 -04:00
Adding manual test feature to testbench -This is as far as I go with fufu testing (random next) -Add basic test for cleaning up reads/writes -104 bit packet format for driving transactions, very useful 2015-04-18 16:14:53 -04:00			`#a sorry hack, too tired to get it right, please fix...`
			`TRANS=$(wc -l test.memh)`
			`TRANS=${TRANS:0:3}`
			`#RANDOM TEST`
Removing hack on rx clock 2015-09-30 13:00:14 -04:00			`iverilog -I../hdl -I../../emailbox/hdl -f elink.cmd -DMANUAL -DTRANS=$TRANS -DTESTNAME=test.memh -DTARGET_XILINX -DSIM`
Adding manual test feature to testbench -This is as far as I go with fufu testing (random next) -Add basic test for cleaning up reads/writes -104 bit packet format for driving transactions, very useful 2015-04-18 16:14:53 -04:00			`#iverilog -f elink.cmd -DAUTO`
Adding fofo environment for elink to check for broken signals. Too many stub modules to be practical..next need sim models 2014-12-14 22:17:23 -05:00
			`#Running sim`
			`./a.out`