oh/xilibs/dv/OBUFTDS.v

module OBUFTDS (/*AUTOARG*/
   // Outputs
   O, OB,
   // Inputs
   I, T
   );

   parameter IOSTANDARD=0;
   parameter SLEW=0;
   
   input I;    //input
   input T;    //tristate signal
   output O;   //output
   output OB;  //output_bar

   assign O  = T ? 1'bz : I;
   assign OB = T ? 1'bz : ~I;
   
   
endmodule // OBUFTDS
Adding stubs files for xilinx IP Goal is to create models for all of these 2014-12-14 22:21:01 -05:00			`module OBUFTDS (/AUTOARG/`
			`// Outputs`
			`O, OB,`
			`// Inputs`
			`I, T`
			`);`

			`parameter IOSTANDARD=0;`
			`parameter SLEW=0;`

Xilinx models -adding ODDR model -configuring the ecfg (rx/tx/clk) in testbench 2015-04-15 17:54:19 -04:00			`input I; //input`
			`input T; //tristate signal`
			`output O; //output`
			`output OB; //output_bar`
Adding stubs files for xilinx IP Goal is to create models for all of these 2014-12-14 22:21:01 -05:00
			`assign O = T ? 1'bz : I;`
			`assign OB = T ? 1'bz : ~I;`


			`endmodule // OBUFTDS`